Memory cell with reduced parasitic capacitance and method of manufacturing the same
US-2024334680-A1 · Oct 3, 2024 · US
USRE45554E · US · E1
| Field | Value |
|---|---|
| Publication number | US-RE45554-E |
| Application number | US-201414297298-A |
| Country | US |
| Kind code | E1 |
| Filing date | Jun 5, 2014 |
| Priority date | Apr 11, 2011 |
| Publication date | Jun 9, 2015 |
| Grant date | Jun 9, 2015 |
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Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal channel.
Opening claim text (preview).
What is claimed is: 1. A method of making a monolithic three dimensional NAND string, comprising: forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises a conductive or semiconductor control gate material and wherein the second material comprises a first sacrificial material; etching the stack to form a back side opening in the stack; depositing a second sacrificial material in the back side openin…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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