Most connection method for egress port selection in a high port count switch

Patent metadata

Field	Value
Publication number	US-9998403-B2
Application number	US-201514928742-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Nov 25, 2014
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A switch according to the present invention can have a number of ports in an ASIC greater than the ASIC clock speed divided by the network protocol rate. The switch ASIC contains multiple blocks, each block having a number of ports equal to the ASIC clock speed divided the packet rate of the protocol. Each block has a number of queues equal to the total number of ports on the ASIC to receive packets. The queues are scheduled from each block into a number of outputs equal to the number of blocks. The outputs of each block are received by a scheduler which evaluates the packets available at the outputs of each block to determine the combination of outputs which provides the most connections that are ready for transmission. The combination with the most connections is then utilized to provide packets to the egress section of each block.

First claim

The invention claimed is:

1. A network switch ASIC comprising:
M times N input ports conforming to a given networking protocol;
M times N output ports conforming to the given networking protocol;
a plurality of M packet processors and of M egress transmission logic blocks, wherein each packet processor has N ports coupled to N input ports and each egress transmission logic block has N ports coupled to N output ports, wherein each packet processor has M outputs and each egress transmission logic block has one input, wherein each one of the packet processor M outputs of a given packet processor is corresponded to a different one of the egress transmission logic block inputs, wherein N is substantially equal to an ASIC clock speed divided by a number of packets per second that each port can process based on the given network protocol, and wherein M is greater than one; and
a scheduler coupled to the plurality of M packet processors and M egress transmission logic blocks, wherein the scheduler is configured to receive the M outputs of each of the packet processors and provide the input of each egress transmission logic block.

2. The network switch ASIC of claim 1 , wherein the M outputs of each packet processor indicate the availability of a packet to be transmitted by a respective egress transmission logic block.

3. The network switch ASIC of claim 1 , wherein the scheduler is further configured to:
determine a plurality of combinations of the M outputs of the packet processors to determine which of the M outputs of each of the packet processors are provided to each egress transmission logic block; and
select one of the combinations based on the number of connections associated with each of the combinations.

4. The network switch ASIC of claim 3 , wherein the selected combination provides the most connections.

5. The network switch ASIC of claim 4 , wherein if at least two of the combinations provide the most connections, the scheduler is further configured to perform a round robin selection between the at least two combinations of outputs.

6. The network switch ASIC of claim 3 , wherein each packet processor includes M time N queues for receiving packets, the queues grouped in M groups, each group providing one of the M outputs of the packet processor, and
wherein the number of connections for each M outputs of each packet processor is based on whether one or more queues within each of the M groups in the packet processor are ready to forward data packets and the corresponding destination ASIC egress port is available.

7. The network switch ASIC of claim 1 , wherein each packet processing includes:
M time N queues for receiving packets, the queues grouped in M groups, each group providing one of the M outputs of the packet processor; and
a plurality of M arbiters, one arbiter associated with each group to determine the queue of the group to provide the output for the group.

8. The network of ASIC of claim 1 , wherein the given network protocol is 10 Gigabit per second Ethernet.

9. The network of ASIC of claim 8 , wherein the ASIC clock speed is 480 MHz, N has a value of 32 and M has a value of 4.

10. A network switch comprising:
a control component including:
a processor having an output; and
a memory coupled to the processor, the memory including non-volatile memory for storing instructions executed by the processor and volatile memory for use by the processor;
M times N switch input ports conforming to a given networking protocol;
M times N switch output ports conforming to the given networking protocol; and
switch custom integrated circuit including:
M times N circuit input ports coupled to the M times N switch input ports;
M times N circuit output ports coupled to the M times N switch output ports;
a plurality of M packet processors and of M egress transmission logic blocks, wherein each packet processor has N ports coupled to N circuit input ports and each egress transmission logic block has N ports coupled to N circuit output ports, wherein each packet processor has M outputs and each egress transmission logic block has one input, wherein each one of the packet processor M outputs of a given packet processor is corresponded to a different one of the egress transmission logic block inputs, wherein N is substantially equal to an integrated circuit clock speed divided by a number of packets per second that each port can process based on the given network protocol, and wherein M is greater than one; and
a scheduler coupled to the plurality of M packet processors and M egress transmission logic blocks, wherein the scheduler is configured to receive the M outputs of each of the packet processors and provide the input of each egress transmission logic block.

11. The network switch of claim 10 , wherein each M packet processor comprises a plurality of M times N queues for receiving incoming packets.

12. The network switch of claim 10 , wherein the M outputs of each packet processor indicate the availability of a packet to be transmitted by a respective egress transmission logic block.

13. The network switch of claim 10 , wherein the scheduler is further configured to:
determine a plurality of combinations of the M outputs of the packet processors to determine which of the M outputs of each of the packet processors are provided to each egress transmission logic block; and
select one of the combinations based on the number of connections associated with each of the combinations.

14. The network switch of claim 13 , wherein the selected combination provides the most connections.

15. The network switch of claim 14 , wherein if at least two of the combinations provide the most connections, the scheduler is further configured to perform a round robin selection between the at least two combinations of outputs.

16. The network switch of 13 , wherein each packet processor includes M time N queues for receiving packets, the queues grouped in M groups, each group providing one of the M outputs of the packet processor, and
wherein the number of connections for each M outputs of each packet processor is based on whether one or more queues within each of the M groups in the packet processor are ready to forward data packets and the corresponding destination ASIC egress port is available.

17. The network switch ASIC of claim 10 , wherein each packet processing includes:
M time N queues for receiving packets, the queues grouped in M groups, each group providing one of the M outputs of the packet processor; and
a plurality of M arbiters, one arbiter associated with each group to determine the queue of the group to provide the output for the group.

18. A method comprising:
receiving a plurality of data packets from M times N input ports;
routing the data packets to M packet processors that each include N input ports and M output ports, wherein N is determined from an maximum clock speed of a packet processing custom integrated circuit divided by the maximum data rate of each of the input ports;
scheduling the data packets for forwarding from the M packet processors to M egress transmission logic blocks that each include one input port and N output ports; and
forwarding the scheduled data packets out M time N output ports,
wherein each one of the packet processor M outputs of a given packet processor is corresponded to a different one of the egress transmission logic block inputs, and
wherein M is greater than one.

19. The method of claim 18 , wherein each packet processor has M outputs and wherein scheduling the data pa

Assignees

• Brocade Comm Systems Inc
• Brocade Communications Systems LLC

Inventors

• Ko Kung-Ling
• Nguyen Tony
• Thein Ye

Classifications

• H04L49/352 Primary

  Gigabit ethernet switching [GBPS] · CPC title