PLL post divider phase continuity

Patent metadata

Field	Value
Publication number	US-9998129-B1
Application number	US-201715711962-A
Country	US
Kind code	B1
Filing date	Sep 21, 2017
Priority date	Sep 21, 2017
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

First claim

We claim:

1. A system, comprising:
a feedback divider for a fractional-N phase-locked loop (PLL), wherein the feedback divider is configured to divide a PLL output signal for the fractional-N PLL to form a divided feedback clock signal;
a pulse swallower circuit configured to remove a pulse from the PLL output signal responsive to an edge for the divided feedback clock signal to form a modified PLL output signal having a missing pulse;
a post divider for post dividing the modified PLL output signal to form a post divided output signal;
a clock recovery circuit configured to assert a recovered divided feedback clock signal responsive to the missing pulse in the modified PLL output signal; and
a sampling circuit configured to sample the post divided output signal responsive to the assertion of the recovered divided feedback clock signal.

2. The system of claim 1 , further comprising:
a digital phase corrector circuit configured to receive a sample of the post divided output signal from the sampling circuit at a first time to determine a first phase relationship between the post divided output signal and the divided feedback clock signal.

3. The system of claim 2 , wherein the digital phase corrector circuit is further configured to receive another sample of the post divided output signal from the sampling circuit at a second time to determine a second phase relationship between the post divided output signal and the divided feedback clock signal.

4. The system of claim 3 , wherein the second time is after the first time.

5. The system of claim 3 , wherein the first time is prior to a sleep mode of operation for the fractional-N PLL and wherein the second time is after a termination of the sleep mode of operation for the fractional-N PLL, and wherein the digital phase corrector circuit is further configured to adjust a division by the feedback divider to maintain a phase continuity for the post divided output signal when the first phase relationship does not equal the second phase relationship.

6. The system of claim 3 , wherein the post divider is a local oscillator post divider.

7. The system of claim 3 , wherein the fractional-N PLL includes:
a phase control circuit configured to perform a phase accumulation, wherein the feedback divider is configured to divide an output clock signal by an integer divisor that is adjusted responsive to the phase accumulation to form the divided feedback clock signal; and
an oscillator configured to drive the PLL output signal at an output frequency responsive to a control signal so that the PLL output signal is phase aligned with a reference clock signal.

8. The system of claim 7 , wherein the phase control circuit further includes:
a delta-sigma modulator; and
an adder configured to add an output from the delta-sigma modulator and an output from the digital phase corrector circuit, wherein the feedback divider is further configured to adjust the integer divisor by a sum signal from the adder.

9. The system of claim 7 , further comprising:
a phase detector configured to compare the divided feedback clock signal to the reference clock signal to detect whether the divided feedback clock signal is leading or lagging the reference clock signal.

10. The system of claim 9 , further comprising:
a charge pump configured to charge or discharge a charge pump output signal responsive to the detection by the phase detector; and
a loop filter configured to filter the charge pump output signal to form a control voltage, wherein the oscillator is a voltage-controlled oscillator configured to be responsive to the control voltage.

11. The system of claim 1 , wherein the pulse swallower circuit comprises a first register and a second register that are both configured to be clocked by the PLL output signal.

12. The system of claim 11 , wherein the pulse swallower circuit further comprises:
a NAND gate configured to NAND a data output signal from the first register with a data output signal from the second register.

13. The system of claim 12 , wherein the pulse swallower circuit further comprises:
a first inverter configured to invert the PLL output signal;
a second inverter configured to invert an output signal from the first inverter to form the modified PLL output signal; and
a transistor coupled between a ground node for the second inverter and ground, wherein the transistor is configured to switch off responsive to a discharge of an output signal from the NAND gate.

14. A method of sampling the phase of a post divided output signal, comprising:
removing a pulse from a phase-locked loop (PLL) output signal for a fractional-N PLL responsive to an edge of a divided feedback clock signal to form a modified PLL output signal having a missing pulse;
dividing the modified PLL output signal in a post divider to form the post divided output signal; and
at a first time, sampling the post divided output signal responsive to a detection of the missing pulse in the modified PLL output signal to determine a first phase relationship between the post divided output signal and the divided feedback clock signal.

15. The method of claim 14 , further comprising:
at a second time subsequent to the first time, sampling the post divided output signal responsive to a detection of the missing pulse in the modified PLL output signal to determine a second phase relationship between the post divided output signal and the divided feedback clock signal.

16. The method of claim 15 , further comprising:
adjusting a feedback division in the fractional-N PLL for forming the divided feedback clock when the second phase relationship does not equal the first phase relationship to maintain a phase continuity for the post divided output signal with the first phase relationship.

17. The method of claim 15 , further comprising shutting down the fractional-N PLL and the post divider during a period between the first time and the second time.

18. A system, comprising:
a feedback divider for a fractional-N phase-locked loop (PLL), wherein the feedback divider is configured to divide a PLL output signal from the fractional-N PLL to form a divided feedback clock signal;
a pulse swallower circuit configured to remove a pulse from the PLL output signal responsive to an edge for the divided feedback clock signal to form a modified PLL output signal with a missing pulse;
a post divider for post dividing the modified PLL output signal to form a post divided output signal; and
means for sampling the post divided output signal responsive to the missing pulse in modified PLL output signal to determine a phase relationship between the post divided output signal and the divided feedback clock signal.

19. The system of claim 18 , further comprising:
a phase control circuit configured to perform a phase accumulation, wherein the feedback divider is configured to divide the PLL output signal by an integer divisor that is adjusted responsive to the phase accumulation to form the divided feedback clock signal; and
an oscillator configured to drive the PLL output signal at an output frequency responsive to a control signal so that the PLL output signal is phase aligned with a reference clock signal.

20. The system of claim 19 , further comprising:
a phase detector configured to compare the divided feedback clock signal to the reference clock signal to detect whether the divided feedback clock signal is leading or lagging the reference clock signal.

Assignees

• Qualcomm Inc

Inventors

• Zhuang Jingcheng
• Hu Jianyun
• Paul Animesh
• Chen Xinhua
• Bossu Frederic

Classifications

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/1976 Primary

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/1803 Primary

  the counter or frequency divider being connected to a cycle or pulse swallowing circuit · CPC title