System and method for variable impedance gate driver

Patent metadata

Field	Value
Publication number	US-9998110-B2
Application number	US-201615344316-A
Country	US
Kind code	B2
Filing date	Nov 4, 2016
Priority date	Nov 4, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

In accordance with an embodiment, a circuit including: a gate driver coupled to a first supply terminal and to an output terminal, the output terminal configured to be coupled to a gate of a switching transistor via an inductive element, the gate driver configured to receive a switching signal; provide a first gate activation voltage at the output terminal with a first output resistance when the switching signal transitions from a first state to a second state; provide the first gate activation voltage at the output terminal with a second output resistance after a first time of providing the first gate activation voltage at the output terminal with the first output resistance, the second output resistance being larger than the first output resistance; and provide a first gate deactivation voltage at the output terminal when the switching signal transitions from the second state to the first state.

First claim

What is claimed is:

1. A circuit comprising:
a gate driver coupled to a first supply terminal and to an output terminal, the output terminal configured to be coupled to a gate of a switching transistor via an inductive element, the gate driver configured to
receive a switching signal;
provide a first gate activation voltage at the output terminal with a first output resistance when the switching signal transitions from a first state to a second state;
provide the first gate activation voltage at the output terminal with a second output resistance after a first time of providing the first gate activation voltage at the output terminal with the first output resistance, the second output resistance being larger than the first output resistance; and
provide a first gate deactivation voltage at the output terminal when the switching signal transitions from the second state to the first state.

2. The circuit of claim 1 , wherein the first time is longer than a time from providing the first gate activation voltage at the output terminal with the first output resistance until a drain voltage of the switching transistor begins to transition as a result of the first gate activation voltage.

3. The circuit of claim 2 , wherein the first time is shorter than a transition time of the switching transistor, wherein the transition time of the switching transistor comprises phases 1, 2, 3 and 4 of a switching transition.

4. The circuit of claim 1 , wherein
the gate driver comprises a first switch coupled to the first supply terminal and to the output terminal,
providing the first gate activation voltage at the output terminal with the first output resistance comprises closing the first switch,
providing the first gate activation voltage at the output terminal with the second output resistance comprises increasing a resistance of a load path of the first switch, and
providing the first gate deactivation voltage comprises opening the first switch.

5. The circuit of claim 4 , wherein the first switch comprises a transistor.

6. The circuit of claim 4 , further comprising a controller coupled to the first switch, the controller configured to
close the first switch,
increase the resistance of the load path of the first switch, and
open the first switch.

7. The circuit of claim 1 , wherein the gate driver is further coupled to a second supply terminal, the gate driver further configured to
provide a second gate activation voltage at the output terminal with a third output resistance when the switching signal transitions from the second state to the first state,
provide the second gate activation voltage at the output terminal with a fourth output resistance after a second time of providing the second gate activation voltage at the output terminal with the third output resistance, the fourth output resistance being larger than the third output resistance, and
provide a second gate deactivation voltage at the output terminal when the switching signal transitions from the first state to the second state.

8. The circuit of claim 7 , wherein
the gate driver comprises
a first switch coupled to the first supply terminal and to the output terminal, and
a second switch coupled to the second supply terminal and to the output terminal,

providing the first gate activation voltage at the output terminal with the first output resistance comprises closing the first switch,
providing the first gate activation voltage at the output terminal with the second output resistance comprises increasing a resistance of a load path of the first switch, and
providing the first gate deactivation voltage comprises opening the first switch,
providing the second gate activation voltage at the output terminal with the third output resistance comprises closing the second switch,
providing the second gate activation voltage at the output terminal with the fourth output resistance comprises increasing a resistance of a load path of the second switch, and
providing the second gate deactivation voltage comprises opening the second switch.

9. The circuit of claim 8 , further comprising a controller coupled to the first switch and to the second switch, the controller configured to
close the first switch,
increase the resistance of the load path of the first switch, and
open the first switch,
close the second switch,
increase the resistance of the load path of the second switch, and
open the second switch.

10. The circuit of claim 9 , wherein the controller increases the resistance of the load path of the first switch after the first time of closing the first switch.

11. The circuit of claim 1 , wherein the first time is shorter than a resonance period of a resonance tank formed between an inductance in series with the output terminal and an equivalent capacitance at the output terminal.

12. The circuit of claim 1 , wherein the gate driver comprises:
a first switch coupled to the first supply terminal and to the output terminal;
a second switch coupled to the first supply terminal and to the output terminal; and
a first resistive element in series with the second switch, wherein the circuit further comprises a controller coupled to the first switch and to the second switch, the controller configured to
close the first switch when providing the first gate activation voltage at the output terminal with the first output resistance,
close the second switch and open the first switch when providing the first gate activation voltage at the output terminal with the second output resistance, and
open the first switch and the second switch when providing the first gate deactivation voltage at the output terminal.

13. The circuit of claim 12 , wherein the first resistive element comprises a first resistor.

14. The circuit of claim 12 , wherein the first resistive element comprises a first transistor.

15. The circuit of claim 12 , wherein the first switch and the second switch are closed simultaneously.

16. The circuit of claim 1 , wherein the switching signal comprises a PWM signal.

17. The circuit of claim 1 , further comprising a first power supply coupled to the first supply terminal and to a second supply terminal, the second supply terminal configured to be coupled to a source of the switching transistor.

18. The circuit of claim 1 , further comprising:
the switching transistor; and
the inductive element.

19. A method of controlling a power MOSFET comprising:
receiving a switching signal;
turning on a first low resistance path coupled between a first power supply and a gate of the power MOSFET when the switching signal transitions from a first state to a second state;
turning on a first resistive path coupled between the first power supply and the gate of the power MOSFET after a first time from turning on the first low resistance path;
turning off the first low resistance path after a second time from turning on the first low resistance path; and
turning off the first resistive path when the switching signal transitions from the second state to the first state.

20. The method of claim 19 further comprising:
turning on a second low resistance path coupled between a second power supply and the gate of the power MOSFET when the switching signal transitions from the second state to the first state;
turning on a second resistive path coupled between the second power supply and the gate of the power MOSFET after a third time from turning on the second low resistance path;
turning off the second low resistance path af

Assignees

• Infineon Technologies Austria Ag

Inventors

• Zojer Bernhard

Classifications

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/163 Primary

  Soft switching · CPC title