Noise filter

US9998084B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9998084-B2
Application numberUS-201615205350-A
CountryUS
Kind codeB2
Filing dateJul 8, 2016
Priority dateJan 17, 2014
Publication dateJun 12, 2018
Grant dateJun 12, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A front-surface-side 3-terminal capacitor and a rear-surface-side 3-terminal capacitor are disposed respectively on a front surface and a rear surface of a circuit substrate at opposing positions. A first outer terminal and a second outer terminal of the front-surface-side 3-terminal capacitor are electrically connected to hot-side conductor patterns and, respectively. Third outer terminals and of the rear-surface-side 3-terminal capacitor are electrically connected to ground-side conductor patterns and, respectively. Third outer terminals and of the front-surface-side 3-terminal capacitor are electrically connected to a first outer terminal and a second outer terminal of the rear-surface-side 3-terminal capacitor by employing vias and, respectively. The front-surface-side 3-terminal capacitor and the rear-surface-side 3-terminal capacitor are thereby electrically connected in series.

First claim

Opening claim text (preview).

The invention claimed is: 1. A noise filter comprising: first and second 3-terminal capacitors mounted to a circuit substrate that includes a hot-side conductor pattern and a ground-side conductor pattern, each of the first and second 3-terminal capacitors including: a bare chip body, a through electrode disposed inside the bare chip body, an inner electrode disposed inside the bare chip body in an opposing relation to the through electrode, a first outer terminal and a second outer terminal disposed respectively on opposite end surfaces of the bare chip body and electrically connected to the through electrode, and at least one third outer terminal disposed on lateral surfaces of the bare chip body and electrically connected to the inner electrode; the first and second 3-terminal capacitors being respectively disposed on a front surface and a rear surface of the circuit substrate at opposing positions, one of the hot-side conductor pattern and the ground-side conductor pattern is electrically connected to the first outer terminal and the second outer terminal of the first 3-terminal capacitor that is disposed on the front surface of the circuit substrate, the other of the hot-side conductor pattern and the ground-side conductor pattern is directly and electrically connected to the at least one third outer terminal of the second 3-terminal capacitor that is disposed on the rear surface of the circuit substrate, the at least one third outer terminal of the first 3-terminal capacitor disposed on the front surface of the circuit substrate is electrically connected to the first outer terminal and the second outer terminal of the second 3-terminal capacitor disposed on the rear surface of the circuit substrate by employing at least one via that is formed in the circuit substrate, and the first 3-terminal capacitor disposed on the front surface of the circuit substrate and the second 3-terminal capacitor disposed on the rear surface of the circuit substrate are electrically connected in series between the hot-side conductor pattern and the ground-side conductor pattern. 2. The noise filter according to claim 1 , wherein the at least one via includes a plurality of the vias is formed in the circuit substrate, and the plurality of vias are used to electrically connect the at least one third outer terminal of the first 3-terminal capacitor disposed on the front surface of the circuit substrate and the first outer terminal of the second 3-terminal capacitor disposed on the rear surface of the circuit substrate, and to electrically connect the at least one third outer terminal of the first 3-terminal capacitor disposed on the front surface of the circuit substrate and the second outer terminal of the second 3-terminal capacitor disposed on the rear surface of the circuit substrate. 3. The noise filter according to claim 1 , wherein the at least one third outer terminal of the first 3-terminal capacitor disposed on the front surface of the circuit substrate and the first outer second terminal and the second outer terminal of the 3-terminal capacitor disposed on the rear surface of the circuit substrate are electrically connected with the at least one via interposed therebetween.

Assignees

Inventors

Classifications

  • Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations · CPC title

  • Terminals · CPC title

  • Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter · CPC title

  • Feed-through capacitors or anti-noise capacitors · CPC title

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

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Frequently asked questions

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What does patent US9998084B2 cover?
A front-surface-side 3-terminal capacitor and a rear-surface-side 3-terminal capacitor are disposed respectively on a front surface and a rear surface of a circuit substrate at opposing positions. A first outer terminal and a second outer terminal of the front-surface-side 3-terminal capacitor are electrically connected to hot-side conductor patterns and, respectively. Third outer terminals and…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H03H1/0007. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 12 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).