Transistor device with segmented contact layer

Patent metadata

Field	Value
Publication number	US-9997608-B2
Application number	US-201715404285-A
Country	US
Kind code	B2
Filing date	Jan 12, 2017
Priority date	Jan 13, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.

First claim

What is claimed is:

1. A transistor device, comprising:
a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer,
wherein the contact layer comprises a plurality of layer sections arranged in a grid layout and separated from each other on all lateral sides by a separation layer,
wherein the plurality of layer sections is electrically connected to an electrode layer disposed above and covering the plurality of layer sections, and
wherein a resistivity of the separation layer is at least 100 times the resistivity of the layer sections.

2. The transistor device of claim 1 , wherein the layer sections are electrically conducting and the separation layer is electrically insulating.

3. The transistor device of claim 1 , wherein the active regions are source regions.

4. The transistor device of claim 1 , wherein each of the plurality of layer sections is electrically connected to the active device region of at least one respective device cell.

5. The transistor device of claim 4 , wherein the least one respective device cell comprises two or more device cells.

6. The transistor device of claim 1 , further comprising:
a plurality of source electrodes each connected to an active device region of transistors devices of a respective group of device cells,
wherein each of the layer sections is electrically connected to at least one respective source electrode of the plurality of source electrodes.

7. The transistor device of claim 6 , further comprising:
a plurality of electrically conducting segments arranged between the semiconductor body and the contact layer,
wherein each of the electrically conducting segments is connected to at least two respective source electrodes, and
wherein each of the layer sections is connected to at least two respective electrically conducting segments.

8. The transistor device of claim 6 , wherein device cells connected to different layer sections share one body region.

9. The transistor device of claim 6 , wherein device cells connected to different layer sections have separate body regions.

10. The transistor device of claim 1 , wherein each of the plurality of device cells further comprises a gate electrode.

11. The transistor device of claim 10 , wherein the gate electrodes of the plurality of device cells are connected to a common gate node.

12. The transistor device of claim 10 , further comprising:
a drive circuit connected to the common gate node,
wherein the drive circuit is integrated in the semiconductor body.

13. The transistor device of claim 1 , wherein the contact layer comprises at least one of a metal, a metal alloy or a metal compound.

14. The transistor device of claim 1 , further comprising:
a solder layer on the contact layer, wherein the electrode layer is arranged on the solder layer.

15. The transistor device of claim 1 , wherein the resistivity of the layer sections is below 1E−6 Ω·m.

16. The transistor device of claim 15 , wherein the resistivity of the layer sections is below 5E−6 Ω·m.

17. The transistor device of claim 16 , wherein the resistivity of the layer sections is below 5E−8 Ω·m.

18. The transistor device of claim 1 , wherein the resistivity of the separation layer is higher than 1E2 Ω·m.

19. The transistor device of claim 1 , wherein the resistivity of the separation layer is higher than 1E6 Ω·m.

20. The transistor device of claim 1 , wherein the resistivity of the separation layer is at least 1000 times the resistivity of the layer sections.

Assignees

• Infineon Technologies Ag

Inventors

• Koepp Karoline
• Gietler Herbert

Classifications

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H01L29/401

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic

• H01L29/41741

  Electricity · mapped topic

• H01L29/4238 Primary

  Electricity · mapped topic