Memory device

Patent metadata

Field	Value
Publication number	US-9997569-B2
Application number	US-201615227053-A
Country	US
Kind code	B2
Filing date	Aug 3, 2016
Priority date	Aug 6, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.

First claim

What is claimed is:

1. A memory device, comprising:
a first electrode including a first element including at least one selected from a group consisting of silver, copper, nickel, cobalt, and aluminum;
an amorphous silicon electrode;
a first layer provided between the first electrode and the amorphous silicon electrode, the first layer including a compound including silicon and oxygen; and
a second layer provided between the first layer and the amorphous silicon electrode, the second layer including a first region and a second region, the second region being provided between the first region and the amorphous silicon electrode, the second region physically contacting the first region and the amorphous silicon electrode, the first region including nitrogen and at least one selected from a group consisting of titanium, tungsten, and tantalum, the second region including a second element,
a standard electrode potential of the second element being lower than a standard electrode potential of the first element,
the second region including nitrogen and a concentration of nitrogen in the first region being higher than a concentration of nitrogen in the second region.

2. The device according to claim 1 , wherein the first region includes at least one selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, and tantalum silicon nitride.

3. The device according to claim 1 , wherein the second element includes at least one selected from the group consisting of titanium, zirconium, aluminum, tantalum, and iron.

4. The device according to claim 1 , wherein the first element includes silver.

5. The device according to claim 1 , wherein the second element includes titanium.

6. The device according to claim 1 , wherein an electrical resistance between the first electrode and the amorphous silicon electrode is a first value when a voltage positive with respect to the amorphous silicon electrode is applied to the first electrode, and the electrical resistance is a second value when a voltage negative with respect to the amorphous silicon electrode is applied to the first electrode, the second value is higher than the first value.

7. The device according to claim 1 , further comprising:
a first interconnect extending in a first direction, the first interconnect being electrically connected to the first electrode, the first direction intersecting a direction from the second layer toward the first layer; and
a second interconnect extending in a second direction, the second interconnect being electrically connected to the second electrode, the second direction intersecting the first direction and intersecting the direction from the second layer toward the first layer.

8. The device according to claim 1 , wherein the second region does not include silicon.

9. A memory device, comprising:
a first electrode including silver;
an amorphous silicon electrode;
a first layer provided between the first electrode and the amorphous silicon electrode, the first layer including a compound including silicon and oxygen; and
a second layer provided between the first layer and the amorphous silicon electrode, the second layer including a first region and a second region, the second region being provided between the first region and the amorphous silicon electrode, the second region physically contacting the first region and the amorphous silicon electrode, the first region including nitrogen and titanium, the second region including nitrogen and titanium,
a concentration of nitrogen in the first region being higher than a concentration of nitrogen in the second region.

10. The device according to claim 9 , wherein the second region does not include silicon.

Assignees

• Toshiba Memory Corp

Inventors

• Yamaguchi Marina
• Fujii Shosuke
• Kamimuta Yuuichi
• Ishikawa Takayuki
• Saitoh Masumi

Classifications

• H01L27/2463

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic

• H01L27/249 Primary

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic