Vertical memory devices

Patent metadata

Field	Value
Publication number	US-9997534-B2
Application number	US-201615155732-A
Country	US
Kind code	B2
Filing date	May 16, 2016
Priority date	May 19, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate;
a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate;
a semiconductor pattern extending from the protrusion to the substrate; and
gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel,
wherein a portion of the semiconductor pattern and a portion of the protrusion are equidistant from the top surface of the substrate in a perpendicular direction with respect to the top surface of the substrate.

2. The vertical memory device of claim 1 , wherein the semiconductor pattern includes at least one of polysilicon, amorphous silicon and single crystalline silicon.

3. The vertical memory device of claim 1 , where n the semiconductor pattern includes:
a horizontal semiconductor pattern physically contacting the protrusion; and
a vertical semiconductor pattern protruding from the top surface of the substrate and physically contacting the horizontal semiconductor pattern.

4. The vertical memory device of claim 3 , further comprising an impurity region at an upper portion of the vertical semiconductor pattern,
wherein a lowermost portion of the impurity region is farther from the top surface of the substrate than a lowermost portion of the channel.

5. The vertical memory device of claim 3 , wherein the protrusion includes a first protrusion and a second protrusion spaced apart from each other in the vertical direction.

6. The vertical memory device of claim 5 , wherein the horizontal semiconductor pattern includes a first horizontal semiconductor pattern and a second horizontal semiconductor pattern physically contacting the first protrusion and the second protrusion, respectively, and
wherein the vertical semiconductor pattern physically contacts each of the first horizontal semiconductor pattern and the second horizontal semiconductor pattern.

7. The vertical memory device of claim 6 , further comprising an impurity region at an upper portion of the vertical semiconductor pattern adjacent to the second horizontal semiconductor pattern,
wherein a lowermost portion of the impurity region is farther from the top surface of the substrate than a lowermost portion of the channel.

8. The vertical memory device of claim 1 , further comprising a dielectric layer structure on an outer sidewall of the channel,
wherein a portion of the dielectric layer structure covers a bottom surface of the channel and a bottom surface of the protrusion.

9. The vertical memory device of claim 8 , further comprising a lower insulation layer on the top surface of the substrate,
wherein the portion of the dielectric layer structure is on the lower insulation layer.

10. A vertical memory device, comprising:
a substrate on which a plurality of lower insulation patterns are arranged in a third direction in parallel with atop surface of the substrate such that adjacent ones of the plurality of lower insulation patterns are spaced apart from each other by an opening through which the substrate is partially exposed;
a semiconductor pattern extending in the third direction around a lateral portion of a first lower insulation pattern of the plurality of lower insulation patterns and making contact with the substrate in the opening;
gate lines stacked over the plurality of lower insulation patterns and spaced apart from each other in a first direction vertically with respect to the top surface of the substrate; and
a channel extending through the gate lines in the first direction and having a ring-shaped protrusion that expands outwards, from a lower portion of the channel in a second direction crossing the first direction and the third direction, the ring-shaped protrusion making contact with the semiconductor pattern under a lowermost line of the gate lines.

11. The vertical memory device of claim 10 , wherein the semiconductor pattern comprises:
a horizontal semiconductor pattern disposed on a top surface of the first lower insulation pattern and making contact with the ring-shaped protrusion; and
a vertical semiconductor pattern disposed on the substrate exposed through the opening and making contact with the horizontal semiconductor pattern.

12. The vertical memory device of claim 11 , further comprising an impurity region at an upper portion of the vertical semiconductor pattern and making contact with the horizontal semiconductor pattern.

13. The vertical memory device of claim 11 , wherein the ring-shaped protrusion comprises a first protrusion and a second protrusion that are spaced apart from each other in the first direction by a separation layer pattern.

14. The vertical memory device of claim 13 , wherein the horizontal semiconductor pattern comprises a first horizontal semiconductor pattern and a second horizontal semiconductor pattern that are spaced apart from each other in the first direction by the separation layer pattern and make contact with the first protrusion and the second protrusion, respectively, and wherein the vertical semiconductor pattern makes contact with the first horizontal semiconductor pattern, and the second horizontal semiconductor pattern, and the separation layer pattern.

15. The vertical memory device of claim 14 , further comprising an impurity region at an upper portion of the vertical semiconductor pattern and making contact with the second horizontal semiconductor pattern.

16. The vertical memory device of claim 15 , wherein the vertical semiconductor pattern, the second horizontal semiconductor pattern, and the second protrusion of the channel provide an electron transfer path between the impurity region and the channel, and
wherein the vertical semiconductor pattern, the first horizontal semiconductor pattern, and the first protrusion of the channel provide a hole transfer path between the channel and the substrate.

17. The vertical memory device of claim 13 , wherein the separation layer pattern includes a silicon-oxide based material.

18. The vertical memory device of claim 11 , further comprising a dielectric layer structure on an outer sidewall of the channel such, that the dielectric layer structure makes contact with a bottom surface of the channel and a bottom surface of the ring-shaped protrusion on the first lower insulation pattern.

19. The vertical memory device of claim 18 , wherein the horizontal semiconductor pattern makes contact with the dielectric layer structure and the ring-shaped protrusion of the channel.

Assignees

• Son Yong Hoon
• Kim Kyung Hyun
• Kim Byeong Ju
• Nam Phil Ouk
• Park Kwang Chul
• Sohn Yeon Sil
• Lee Jin I
• Lim Jong Heun
• Jung Won Bong
• Kanamori Kohji
• Samsung Electronics Co Ltd

Inventors

• Son Yong-Hoon
• Kim Kyung-Hyun
• Kim Byeong-Ju
• Nam Phil-Ouk
• Park Kwang Chul
• Sohn Yeon-Sil
• Lee Jin-I
• Lim Jong-Heun
• Jung Won-Bong
• Kanamori Kohji

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title