Monolithic integration of III-V cells for powering memory erasure devices

Patent metadata

Field	Value
Publication number	US-9997475-B2
Application number	US-201614994267-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.

First claim

What is claimed is:

1. A method for making a photovoltaic device, the method comprising:
forming a memory cell including:
providing a silicon substrate comprising a complementary metal-oxide semiconductor (“CMOS”); and
bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate;
forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate; and
forming a memory erasure device connected to the III-V photovoltaic cell,
the III-V photovoltaic cell to generate a current when the III-V photovoltaic cell is exposed to radiation, the current to power the memory erasure device to cause an alteration of a memory state of the memory cell.

2. The method of claim 1 wherein the photovoltaic device is formed from a single crystal chip.

3. The method of claim 1 wherein the III-V photovoltaic cell comprises a Group III element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), and ununtrium (Uut) and a Group V element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and ununpentium (Uup).

4. The method of claim 1 wherein the memory erasure device comprises a reactive material comprising a thin metal film.

5. The method of claim 4 wherein the current generated by the photovoltaic cell triggers an exothermic reaction in the reactive material.

6. The method of claim 5 wherein a heat generated by the exothermic reaction in the reactive material alters the memory state of the memory cell.

7. The method of claim 1 wherein the memory erasure device comprises nickel, aluminum, titanium, copper, palladium, boron, platinum, copper oxide, hafnium oxide, or combinations thereof.

8. The method of claim 1 wherein forming the III-V photovoltaic cell includes epitaxially growing a III-V layer.

9. A method for making a photovoltaic device, the method comprising:
low-temperature bonding of a III-V wafer comprising a thin epitaxial template layer;
selective removal of a sacrificial release layer or full removal of a III-V substrate; deposition and patterning oxide trenches;
selective epitaxial growth of a III-V photovoltaic cell; and planarization and deposition of a transparent conducting layer.

Assignees

• IBM

Inventors

• Rodbell Kenneth
• Shahrjerdi Davood

Classifications

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• G06F2221/2143

  Clearing memory, e.g. to prevent the data from being stolen · CPC title

• Y02E10/544

  Solar cells from Group III-V materials · CPC title

• G06F21/87 Primary

  by means of encapsulation, e.g. for integrated circuits · CPC title

• H01L31/1852

  Electricity · mapped topic