Chip package and method for forming the same

Patent metadata

Field	Value
Publication number	US-9997473-B2
Application number	US-201715409289-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Jan 19, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

First claim

What is claimed is:

1. A chip package, comprising:
a substrate having a first surface and a second surface opposite thereto, wherein the substrate comprises a sensing or device region which is adjacent to the first surface;
a recess in the substrate, wherein the recess extends from the second surface towards the first surface, and is under the sensing or device region;
a redistribution layer extending from the second surface into the recess; and
a protection layer extending from the second surface of the substrate into the recess to cover the redistribution layer on a bottom of the substrate and expose a top portion of the recess.

2. The chip package as claimed in claim 1 , further comprising one or more electronic devices in the recess, wherein the one or more electronic devices are under the sensing or device region and are electrically connected to the redistribution layer in the recess.

3. The chip package as claimed in claim 2 , wherein the one or more electronic devices comprise active devices, passive devices, or combinations thereof.

4. The chip package as claimed in claim 2 , wherein the one or more electronic devices are embedded in the substrate via the recess, so that the one or more electronic devices are surrounded by a portion of the substrate.

5. The chip package as claimed in claim 2 , further comprising an underfill layer that is filled between the one or more electronic devices and a bottom of the recess.

6. The chip package as claimed in claim 2 , wherein the one or more electronic devices are laterally arranged in the recess or vertically stacked in the recess.

7. The chip package as claimed in claim 1 , further comprising another recess formed in the substrate, extending from the second surface toward the first surface, and being under the sensing or device region.

8. The chip package as claimed in claim 7 , further comprising one or more electronic devices embedded in the substrate via the recess and the another recess, so that the one or more electronic devices are surrounded by a portion of the substrate.

9. The chip package as claimed in claim 1 , wherein the protection layer comprises:
a first opening partially exposes the redistribution layer in the recess; and
a second opening partially exposes the redistribution layer on the second surface.

10. The chip package as claimed in claim 9 , further comprising:
a first conductive structure in the first opening and electrically connected to the redistribution layer, wherein the first conductive structure is under the sensing or device region; and
a second conductive structure in the second opening and electrically connected to the redistribution layer.

11. The chip package as claimed in claim 9 , further comprising a second conductive structure in the second opening and electrically connected to the redistribution layer, wherein the redistribution layer in the recess is exposed from the first opening.

12. The chip package as claimed in claim 1 , further comprising:
a conductive pad adjacent to the first surface of the substrate and outside of the sensing or device region; and
an opening in the substrate, wherein the opening extends from the second surface toward the first opening to expose the conductive pad, and wherein the redistribution layer extends from the second surface into the recess so as to be electrically connected to the conductive pad.

13. The chip package as claimed in claim 12 , wherein the recess has a depth that is less than that of the opening and has a size that is greater than that of the opening.

14. The chip package as claimed in claim 12 , wherein the protection layer extends from the second surface of the substrate into the opening, and wherein the protection layer is separated from the redistribution layer on a bottom of the opening and contacts the redistribution layer on a bottom of the recess.

15. A method for forming a chip package, comprising:
providing a substrate having a first surface and a second surface opposite thereto, wherein the substrate comprises a sensing or device region which is adjacent to the first surface;
forming a recess in the substrate, wherein the recess extends from the second surface towards the first surface, and is under the sensing or device region;
forming a redistribution layer extending from the second surface into the recess; and
forming a protection layer on the second surface of the substrate after the formation of the redistribution layer, wherein the protection layer extends into the recess to cover the redistribution layer on a bottom of the recess while exposing a top portion of the recess.

16. The method for forming a chip package as claimed in claim 15 , further comprising forming an opening in the substrate during the formation of the recess, wherein the opening extends from the second surface toward the first opening.

17. The method for forming a chip package as claimed in claim 16 , wherein a conductive pad adjacent to the first surface of the substrate and outside of the sensing or device region, and wherein the method for forming a chip package further comprises extending the opening after the formation of the recess and before the formation of the redistribution layer until the conductive pad is exposed, so that the opening has a depth that is greater than that of the recess.

18. The method for forming a chip package as claimed in claim 1 , further comprising:
forming a first opening in the protection layer to partially expose the redistribution layer in the recess; and
forming a second opening in the protection layer to partially expose the redistribution layer on the second surface.

19. The method for forming a chip package as claimed in claim 18 , further comprising:
forming a first conductive structure in the first opening, wherein the first conductive structure is electrically connected to the redistribution layer and is under the sensing or device region; and
forming a second conductive structure in the second opening, wherein the second conductive structure is electrically connected to the redistribution layer and the recess exposes the first conductive structure after the formation of the first conductive structure and the second conductive structure.

20. The method for forming a chip package as claimed in claim 18 , further comprising forming a second conductive structure in the second opening, wherein after the formation of the second conductive structure, the first opening exposes the redistribution layer in the recess.

21. The method for forming a chip package as claimed in claim 18 , further comprising:
forming a first conductive structure in the first opening, so that an electronic device is bonded on the substrate via the first conductive structure, wherein the electronic device is embedded in the substrate via the recess, so that the electronic device is surrounded by a portion of the substrate; and
forming a second conductive structure in the second opening after the bonding of the electronic device, wherein the second conductive structure is electrically connected to the redistribution layer.

22. The method for forming a chip package as claimed in claim 21 , further comprising filling an underfill layer between the electronic device and the bottom of the substrate prior to the formation of the second conductive structure.

23. The method for forming a chip package as claimed in claim 21 , further comprising performing a dicing process after the bonding of the electronic de

Assignees

• Xintec Inc

Inventors

• Ho Yen-Shih
• Liu Tsang-Yu
• Lin Chia-Sheng
• LAI Chaung-Lin

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title