Support for long channel length nanowire transistors

Patent metadata

Field	Value
Publication number	US-9997472-B2
Application number	US-201715401539-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Jul 13, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

First claim

The invention claimed is:

1. A nanowire device, comprising:
a first semiconductor region on a substrate;
a second semiconductor region on the substrate disposed apart from the first semiconductor region by a distance in the range of about 500 nm to about 2 microns;
at least one nanowire including at least one anchor pad and a plurality of nanowire segments that is connected to the first semiconductor region at one end and to the second semiconductor region at the opposite end, wherein the at least one anchor pad supports the plurality of nanowire segments of the at least one nanowire above the substrate, and wherein the first semiconductor region includes a transistor source and the second semiconductor region includes a transistor drain, and the at least one nanowire forms a device channel between the transistor source and the transistor drain.

2. The device as recited in claim 1 , wherein the plurality of nanowire segments and the anchor pad include a semiconductor material.

3. The device as recited in claim 1 , further comprising a gate dielectric and a gate conductor formed on each of the plurality of nanowire segments.

4. The device as recited in claim 1 , wherein each of the plurality of nanowire segments have a nanowire segment length in the range of about 50 nm to about 300 nm.

5. The device as recited in claim 4 , wherein the at least one anchor pad has a width in the range of about 20 nm to about 50 nm.

6. The device as recited in claim 5 , wherein the at least one anchor pad has a thickness in the range of about 50 nm to about 500 nm.

7. The device as recited in claim 4 , wherein the at least one nanowire is a plurality of parallel nanowires, wherein each of the parallel nanowires is supported along a span by the at least one anchor pad.

8. The device as recited in claim 7 , wherein the at least one anchor pad is a plurality of anchor pads, where each anchor pad is located after a nanowire segment length of about 200 nm.

9. The device as recited in claim 8 , wherein the plurality of nanowire segments and the plurality of anchor pads comprise a device channel having a length of between 500 nm to about 2 microns.

10. A nanowire device, comprising:
a semiconductor source and a semiconductor drain formed on a substrate and separated by a span;
at least one nanowire being suspended over the substrate and being configured to connect the semiconductor to the semiconductor drain as a device channel, wherein each of the at least one nanowire is electrically connected to the semiconductor source by a via and the semiconductor drain by a via, wherein the at least one nanowire includes at least one anchor pad having a width in a range of about 20 nm to about 50 nm and a plurality of nanowire segments; and
a gate dielectric and a gate metal is around each of the plurality of nanowire segments.

11. The device as recited in claim 10 , wherein the plurality of nanowire segments and the at least one anchor pad include a semiconductor material.

12. The device as recited in claim 10 , wherein the at least one anchor pad is a plurality of anchor pads disposed along the span for supporting the at least one nanowire.

13. The device as recited in claim 12 , wherein adjacent anchor pads of the plurality of anchor pads are separated by a distance of at least 200 nm.

14. The device as recited in claim 10 , wherein the at least one nanowire includes a plurality of parallel nanowires, wherein each of the parallel nanowires is supported along the span by each of the at least one anchor pad.

15. The device as recited in claim 10 , wherein the span has a length in a range of about 500 nm to about 2 microns.

16. The device as recited in claim 10 , wherein the at least one nanowire includes a plurality of nanowire segments connected by a plurality of anchor pads.

17. The device as recited in claim 16 , wherein each of the plurality of nanowire segments has a length in a range of about 50 nm to about 300 nm.

18. The device as recited in claim 17 , wherein the plurality of anchor pads support the at least one nanowire, and the plurality of anchor pads are disposed along the device channel with a periodicity equal to the nanowire segments length, such that each of the plurality of nanowire segments is supported by at least one anchor pad.

19. A nanowire device, comprising:
a semiconductor source and a semiconductor drain formed on a substrate and separated by a span; and
at least one nanowire being configured to connect the semiconductor source to the semiconductor drain as a device channel, wherein each of the at least one nanowire is electrically connected to the semiconductor source by a via and the semiconductor drain by a via, wherein the at least one nanowire includes at least one anchor pad and a plurality of nanowire segments, wherein each of the plurality of nanowire segments has a length in range of about 50 nm to about 300 nm, and the plurality of nanowire segments are suspended over the substrate.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Lauer Isaac
• Yamashita Tenko
• Sleight Jeffrey W

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/2914

  Oxides · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/0649

  Electricity · mapped topic