Via structures for thermal dissipation

Patent metadata

Field	Value
Publication number	US-9997428-B2
Application number	US-201514799534-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Jul 14, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a substrate, pluralities of vias disposed in the substrate. The vias are disposed in a hexagonal arrangement.

First claim

We claim:

1. An apparatus, comprising:
a substrate;
a first plurality of tapered vias disposed in the substrate, the first plurality of tapered vias being disposed in a hexagonal arrangement;
a first capture pad disposed beneath the first plurality of tapered vias, the first capture pad having a first width;
a second plurality of tapered vias disposed in the substrate and beneath the first capture pad, the second plurality of tapered vias being disposed in the hexagonal arrangement;
a first contact pad disposed over an upper surface of the substrate, and in direct contact with at least one of the first plurality of tapered vias;
a second capture pad having a second width that is greater than the first width;
a third plurality of tapered vias disposed in the substrate and beneath the second capture pad, the third plurality of tapered vias being disposed in the hexagonal arrangement; and
a second contact pad disposed over a lower surface of the substrate, the second contact pad being in direct contact with at least one of the third plurality of tapered vias.

2. The apparatus as claimed in claim 1 , wherein portions of the substrate are disposed between at least two of the first plurality of tapered vias, and between at least two of the second plurality of tapered vias.

3. The apparatus as claimed in claim 1 , wherein the first capture pad electrically and thermally connects each of the first plurality of tapered vias.

4. The apparatus as claimed in claim 1 , wherein the apparatus further comprises:
a third capture pad; and
a fourth plurality of tapered vias disposed in the substrate and beneath the third capture pad, the fourth plurality of tapered vias being disposed in the hexagonal arrangement.

5. The apparatus as claimed in claim 4 , wherein the third plurality of tapered vias is disposed beneath the third capture pad.

6. The apparatus as claimed in claim 1 , wherein the first capture pad, the first, second and third pluralities of tapered vias, and the second capture pad are disposed in a trapezoidal areal manner.

7. The apparatus as claimed in claim 1 , wherein the first capture pad is substantially aligned with the second capture pad.

8. The apparatus as claimed in claim 1 , wherein each of the tapered vias of the first and second plurality of tapered vias has a height, and a substantially circular cross-section.

9. The apparatus as claimed in claim 8 , wherein a diameter of each of the tapered vias decreases across its height.

10. A semiconductor package, comprising:
an active semiconductor die disposed over first contact pad of the apparatus of claim 1 .

11. The semiconductor package as claimed in claim 10 , wherein
the first contact pad is electrically connected to ground.

12. The semiconductor package as claimed in claim 10 , wherein
the active semiconductor die comprises at least one Group III-V semiconductor device.

13. The semiconductor package as claimed in claim 12 , wherein the at least one Group III-V semiconductor device comprise a heterojunction bipolar transistor (HBT), or a pseudomorphic high electron mobility transistor (pHEMT).

14. An apparatus, comprising:
a substrate;
a first plurality of tapered vias disposed in the substrate, the tapered vias being disposed in a hexagonal arrangement, wherein an areal dimension of each of the first plurality of tapered vias increases or decreases across its height;
a capture pad disposed beneath the first plurality of tapered vias;
a second plurality of tapered vias disposed in the substrate and beneath the capture pad, the second plurality of tapered vias being disposed in the hexagonal arrangement; and
a contact pad disposed over an upper surface of the substrate, and in direct contact with at least one of the first plurality of tapered vias.

15. The apparatus as claimed in claim 14 , wherein an areal dimension of each of the second plurality of tapered vias increases or decreases across its height.

16. The apparatus as claimed in claim 14 , wherein each of the first and second plurality of tapered vias has a height, and a substantially circular cross-section.

17. The apparatus as claimed in claim 14 , wherein portions of the substrate are disposed between at least two of the first plurality of tapered vias, and between at least two of the second plurality of tapered vias.

18. The apparatus as claimed in claim 14 , wherein the capture pad is a first capture pad, and the contact pad is a first contact pad, and the apparatus further comprises:
a second capture pad;
a third plurality of tapered vias disposed in the substrate and beneath the second capture pad, the third plurality of tapered vias being disposed in the hexagonal arrangement; and
a second contact pad disposed over a lower surface of the substrate, the second contact pad being in direct contact with at least one of the third plurality of tapered vias.

19. The apparatus as claimed in claim 14 , wherein the capture pad electrically and thermally connects each of the first plurality of tapered vias.

20. The apparatus as claimed in claim 18 , further comprising:
a third capture pad; and
a fourth plurality of tapered vias disposed in the substrate and beneath the third capture pad, the fourth plurality of tapered vias being disposed in the hexagonal arrangement.

21. The apparatus as claimed in claim 20 , wherein the third plurality of tapered vias is disposed beneath the third capture pad.

22. The apparatus as claimed in claim 18 , wherein the first capture pad has a first width, and the second capture pad has a second width that is greater than the first width.

23. The apparatus as claimed in claim 22 , wherein the first capture pad, the first, second and third pluralities of tapered vias, and the second capture pad are disposed in a trapezoidal areal manner.

24. The apparatus as claimed in claim 18 , wherein the first capture pad has a first width, and the second capture pad has a second width that is approximately the same as the first width.

25. The apparatus as claimed in claim 24 , wherein the first capture pad is substantially aligned with the second capture pad.

26. The apparatus as claimed in claim 24 , wherein the first capture pad is offset relative to the second capture pad.

27. A semiconductor package, comprising:
an active semiconductor die disposed over first contact pad of the apparatus of claim 18 .

28. The semiconductor package as claimed in claim 27 , wherein the first contact pad is electrically connected to ground.

29. The semiconductor package as claimed in claim 27 , wherein the active semiconductor die comprises at least one Group III-V semiconductor device.

30. The semiconductor package as claimed in claim 29 , wherein the at least one Group III-V semiconductor device comprise a heterojunction bipolar transistor (HBT), or a pseudomorphic high electron mobility transistor (pHEMT).

31. An apparatus, comprising:
a substrate;
a first plurality of tapered vias disposed in the substrate, the first plurality of tapered vias being disposed in a hexagonal arrangement;
a first capture pad disposed beneath the first plurality of tapered vias, the first capture pad having a first width;
a second plurality of tapered vias disposed in the substrate and beneath the first capture pad, the second plurality of tapered vias being disp

Assignees

• Avago Technologies General Ip

Inventors

• Maple Marshall
• Alawani Ashish
• Sun Li
• Haney Sarah

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W40/255

  having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title