Fabrication method of a stack of electronic devices

Patent metadata

Field	Value
Publication number	US-9997395-B2
Application number	US-201715616568-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Jun 7, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b) providing a second structure successively including a substrate, an active layer, an intermediate layer, a first semiconducting layer and a porous second semiconducting layer; c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer; d) removing the substrate of the second structure so as to expose the active layer; e) adding dopants to the first semiconducting layer or to the active layer; f) irradiating the first semiconducting layer by a pulse laser so as to thermally activate the corresponding dopants.

First claim

The invention claimed is:

1. A method of fabricating a stack of electronic devices, comprising the following steps:
a) providing a first structure successively comprising a first substrate, a first electronic device, and a dielectric layer;
b) providing a second structure successively comprising a second substrate, an active layer designed to form a second electronic device, an intermediate layer, a first semiconducting layer designed to form a ground plane, and a porous second semiconducting layer;
c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer;
d) removing the second substrate of the second structure so as to expose the active layer;
e) adding dopants to the first semiconducting layer or the active layer;
f) irradiating the first semiconducting layer or the active layer by a pulse laser so as to thermally activate the dopants.

2. The method according to claim 1 , wherein the porous second semiconducting layer presents a free surface in step b), and wherein step b) comprises a step b 1 ) consisting in forming a dielectric layer on said free surface, direct bonding being performed in step c) between the dielectric layer of the first structure and the dielectric layer formed in step b 1 ).

3. The method according to claim 2 , wherein the dielectric layer formed in step b 1 ) is an oxide.

4. The method according to claim 1 , wherein step b) is executed so that the porous second semiconducting layer presents a void ratio comprised between 20% and 80%.

5. The method according to claim 1 , wherein the porous second semiconducting layer is made from porous silicon.

6. The method according to claim 1 , wherein the porous second semiconducting layer presents a thickness comprised between 50 nm and 120 nm.

7. The method according to claim 1 , wherein the second substrate of the second structure is made from semiconductor material.

8. The method according to claim 1 , wherein the dielectric layer of the first structure is made from silicon dioxide.

9. The method according to claim 1 , wherein the dielectric layer of the first structure presents a thickness of more than 60 nm.

10. The method according to claim 1 , wherein the dopants added to the first semiconducting layer in step e) are selected from the group comprising B, In, P, and As.

11. The method according to claim 1 , wherein the second structure provided in step b) comprises an etch stop layer inserted between the second substrate of the second structure and the active layer.

12. The method according to claim 11 , wherein the etch stop layer is made from SiGe.

13. The method according to claim 1 , wherein the intermediate layer provided in step b) is etched after step d) in a selective manner relatively to the active layer and to the first semiconducting layer; and a buried oxide layer is formed instead of and in place of the etched intermediate layer.

14. The method according to claim 13 , wherein the intermediate layer provided in step b) is made from SiGe.

15. A method of fabricating a stack of electronic devices, comprising the following successive steps:
a) providing a first structure successively comprising a first substrate, a first electronic device, and a dielectric layer;
b) providing a second structure successively comprising a second substrate, an active layer designed to form a second electronic device, an intermediate layer, a first semiconducting layer designed to form a ground plane, and a porous second semiconducting layer;
c) bonding the first and second structures by direct bonding between the dielectric layer and the porous second semiconducting layer;
d) removing the second substrate of the second structure so as to expose the active layer;
e) adding dopants to the first semiconducting layer or the active layer;
f) irradiating the first semiconducting layer or the active layer by a pulse laser so as to thermally activate the dopants.

16. A method of fabricating a stack of electronic devices, comprising the following successive steps:
a) providing a first structure successively comprising a first substrate, a first electronic device, and a first dielectric layer;
b) providing a second structure successively comprising a second substrate, an active layer designed to form a second electronic device, an intermediate layer, a first semiconducting layer designed to form a ground plane, and a porous second semiconducting layer presenting a free surface;
b 1 ) forming a second dielectric layer on said free surface:

c) bonding the first and second structures by direct bonding between the first dielectric layer and the second dielectric layer;
d) removing the second substrate of the second structure so as to expose the active layer;
e) adding dopants to the first semiconducting layer or the active layer;
f) irradiating the first semiconducting layer or the active layer by a pulse laser so as to thermally activate the dopants.

Assignees

• Commissariat Energie Atomique

Inventors

• Fenouillet-Beranger Claire
• Gaillard Frédéric-Xavier
• Mathieu Benoit
• Nemouchi Fabrice

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title

• H10P10/12 Primary

  Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914) · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1924 Primary

  with separation/delamination along a porous layer · CPC title