Data register for radiation hard applications

Patent metadata

Field	Value
Publication number	US-9997210-B2
Application number	US-201514671786-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A circuit comprises a data storage element that includes a sampling stage configured to sample a data value, the sampling stage comprising a plurality of p-type devices, wherein at least one of the plurality of p-type devices is non-collinear relative to the other p-type devices, a plurality of n-type devices, wherein at least one of the plurality of n-type devices is non-collinear relative to the other n-type devices, a feedback stage configured to maintain the data value sampled by the sampling stage.

First claim

What is claimed is:

1. A circuit comprising;
a data storage element that includes:
a sampling stage configured to sample a data value, the sampling stage comprising:
a plurality of p-type devices comprising a first p-type device, a second p-type device, and a third p-type device, wherein a source of the first p-type device is connected to a drain of the second p-type device, wherein a source of the second p-type device is connected to a drain of the third p-type device, wherein layout of the circuit is such that at least one of the plurality of p-type devices is non-collinear relative to the other p-type devices,
a plurality of n-type devices comprising a first n-type device, a second n-type device, and a third n-type device, wherein a source of the first n-type device is connected to a drain of the second n-type device, wherein a source of the second n-type device is connected to a drain of the third n-type device, wherein layout of the circuit is such that at least one of the plurality of n-type devices is non-collinear relative to the other n-type devices,
a feedback stage configured to maintain the data value sampled by the sampling stage; and
clocking circuitry configured to generate a first clock signal and a second clock signal, wherein the first clock signal drives at least one p-type device of the plurality of p-type devices and the second clock signal drives at least a different one of the p-type devices of the plurality of p-type devices, wherein the clocking circuitry is further configured to generate a third clock signal and a fourth clock signal, wherein the third clock signal drives at least one n-type device of the plurality of n-type devices and the fourth clock signal drives at least a different one of the n-type devices of the plurality of n-type devices.

2. The circuit of claim 1 , wherein
the second p-type device is configured to receive the data value;
the second n-type device is configured to receive the data value, wherein a drain of the first n-type device is connected to a drain of the first p-type device.

3. The circuit of claim 1 , wherein
the first p-type device is configured to receive the data value;
the first n-type device is configured to receive the data value.

4. The circuit of claim 1 , wherein the feedback stage comprises a clocked inverter, wherein the clocked inverter comprises:
a second plurality of p-type devices comprising a fourth p-type device, a fifth p-type device, and a sixth p-type device, wherein a source of the fourth p-type device is connected to a drain of the fifth p-type device, wherein a source of the fifth p-type device is connected to a drain of the sixth p-type device, wherein at least one of the second plurality of p-type devices is non-collinear relative to the other p-type devices of the second plurality of p-type devices; and
a second plurality of n-type devices comprising a fourth n-type device, a fifth n-type device, and a sixth n-type device, wherein a source of the fourth n-type device is connected to a drain of the fifth n-type device, wherein a source of the fifth n-type device is connected to a drain of the sixth n-type device, wherein at least one of the second plurality of n-type devices is non-collinear relative to the other n-type devices of the second plurality of n-type devices.

5. The circuit of claim 4 , the fourth p-type device is configured to receive an intermediate data value, and wherein the fifth p-type device has a lower voltage threshold than the fourth p-type device.

6. The circuit of claim 5 , wherein the fourth p-type device is connected to an n-type device of the second plurality of n-type devices.

7. The circuit of claim 4 , wherein the fourth n-type device is configured to receive the intermediate data value, and wherein the fifth n-type device has a lower voltage threshold than the fourth n-type device.

8. The circuit of claim 7 , wherein the fourth n-type device is connected to a p-type device of the second plurality of p-type devices.

9. The circuit of claim 4 , wherein the fourth p-type device is configured to receive an intermediate data value and a gate of the fifth p-type device is connected to a bias voltage.

10. The circuit of claim 9 , wherein the fourth p-type device is connected to an n-type device of the second plurality of n-type devices.

11. The circuit of claim 4 , wherein the fourth n-type device is configured to receive the intermediate data value and a gate of the fifth n-type device is connected to a bias voltage.

12. The circuit of claim 4 , wherein the fourth n-type device is configured to receive the intermediate data value, the fourth p-type device is configured to receive the intermediate data value, and a gate of the fourth n-type device is connected to a gate of the fourth p-type device.

13. The circuit of claim 4 , wherein the fourth n-type device is configured to receive the intermediate data value, the fourth p-type device is configured to receive the intermediate data value, and a gate of the fifth n-type device is connected to a gate of the fifth p-type device.

14. The circuit of claim 13 , wherein the fourth p-type device has a lower voltage threshold than the fifth p-type device, and wherein the fourth n-type device has a lower voltage threshold than the fifth n-type device.

15. The circuit of claim 1 , wherein the feedback stage comprise a non-clocked inverter, wherein the non-clocked inverter comprises:
a second plurality of non-collinear p-type devices; and
a second plurality of non-collinear n-type devices.

16. The circuit of claim 1 , wherein the plurality of p-type devices are arranged on the circuit such that a single straight line cannot intersect a sensitive region of at least one of the p-type devices and the plurality of n-type devices are arranged on the circuit such that a single straight line cannot intersect a sensitive region of at least one of the n-type devices.

17. The circuit of claim 1 , wherein the plurality of p-type devices comprises four or more p-type devices.

18. The circuit of claim 1 , wherein the plurality of n-type devices comprises four or more n-type devices.

19. The circuit of claim 1 , wherein the second plurality of p-type devices comprises at least three p-type devices and the second plurality of n-type devices comprises at least three n-type devices.

Assignees

• Honeywell Int Inc

Inventors

• Rabe Robert

Classifications

• H03K3/35625

  using complementary field-effect transistors · CPC title

• H03K19/00338

  In field effect transistor circuits · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title