Display device with reduced number of transistors and its driving method

Patent metadata

Field	Value
Publication number	US-9997109-B2
Application number	US-201615249919-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Dec 21, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A display device including pixel circuit groups containing pixel circuits. The pixel circuit groups each contain: a first transistor whose first terminal is connected to a power source potential line; and a sixth transistor whose control terminal is connected to a first scanning signal line and whose first terminal is connected to an image signal line. The pixel circuit each include: a second transistor whose control terminal is connected to a first node and whose first terminal is connected to a second terminal of the first transistor and a second terminal of the sixth transistor; a third transistor whose first terminal is connected to the first node and whose second terminal is connected to a second terminal of the second transistor; a fourth transistor whose first terminal is connected to the second terminal of the second transistor; and a fifth transistor whose first terminal is connected to the first node.

First claim

What is claimed is:

1. A display device comprising:
a plurality of first scanning signal lines;
a plurality of second scanning signal lines;
a plurality of initialization-controlling signal lines;
a plurality of emission-controlling signal lines;
a plurality of image signal lines intersecting the plurality of first scanning signal lines, the plurality of second scanning signal lines, the plurality of initialization-controlling signal lines, or the plurality of emission-controlling signal lines; and
a plurality of pixel circuit groups electrically connected to any one of the plurality of first scanning signal lines, any one of the plurality of second scanning signal lines, any one of the plurality of initialization-controlling signal lines, and any one of the plurality of emission-controlling signal lines,
wherein each of the plurality of pixel circuit groups comprises:
a plurality of pixel circuits;
a first transistor in which a control terminal is electrically connected to the emission-controlling signal line and a first terminal is electrically connected to a power source potential line; and
a sixth transistor in which a control terminal is electrically connected to the first scanning signal line and a first terminal is electrically connected to the image signal line,

wherein each of the plurality of pixel circuits comprises:
a second transistor in which a control terminal is electrically connected to a first node, and a first terminal is electrically connected to a second terminal of the first transistor and a second terminal of the sixth transistor;
a third transistor in which a first terminal is electrically connected to the first node, a second terminal is electrically connected to a second terminal of the second transistor, and a control terminal is electrically connected to the second scanning signal line;
a fourth transistor in which a first terminal is electrically connected to a second terminal of the sixth transistor, and a control terminal is electrically connected to the emission-controlling signal line;
a fifth transistor in which a first terminal is electrically connected to the first node, a control terminal is electrically connected to the initialization-controlling signal line, and a second terminal is electrically connected to an initialization signal line;
a storage capacitor in which a first terminal is electrically connected to the first node; and
a light-emitting element electrically connected to a second terminal of the fourth transistor, and

wherein each of the plurality of pixel circuit groups is configured so that, in an initialization period:
a signal which turns off the third transistor is supplied to the control terminal of the third transistor; and
a signal which turns on the fifth transistor is supplied to the control terminal of the fifth transistor.

2. The display device according to claim 1 ,
wherein a second terminal of the storage capacitor is electrically connected to a constant potential.

3. The display device according to claim 1 ,
wherein each of the plurality of pixel circuit groups is configured so that, in a writing and threshold compensation period after the initialization period:
a signal which turns off the fifth transistor is supplied to the control terminal of the fifth transistor; and
gradation data is supplied to the image signal line by sequentially turning on the third transistors of the plurality of pixel circuits while supplying the plurality of second scanning signal line with a signal which turns on the sixth transistor.

4. The display device according to claim 3 ,
wherein each of the plurality of pixel circuit groups is configured so that, in an emission period after the writing and threshold compensation period:
the first transistor and the fourth transistor are turned off while supplying the plurality of first scanning signal lines and the plurality of second scanning lines with signals which turn off the sixth transistor and the third transistor; and
a current is flowed in the light-emitting elements to emit light.

5. The display device according to claim 4 ,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are P-channel transistors.

6. The display device according to claim 1 ,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are transistors with the same polarity.

7. A driving method of a display device which includes:
a plurality of pixel circuit groups each comprising:
a first pixel circuit;
a second pixel circuit; and
first and sixth transistors each comprising a first terminal, a second terminal, and a control terminal;

wherein the first pixel circuit and the second pixel circuit in each of the plurality of pixel circuit groups comprise:
a second transistor, a third transistor, a fourth transistor, and a fifth transistor each comprising a control terminal, a first terminal, and a second terminal;
a storage capacitor comprising first and second terminals; and
a light-emitting element; and

wherein, in each of the plurality of pixel circuit groups:
the second terminal of the first transistor is electrically connected to the second terminal of the sixth transistor and the first terminal of the second transistor;
the control terminal of the second transistor is electrically connected to the first terminal of the third transistor, the first terminal of the fifth transistor, and the first terminal of the storage capacitor, and the second terminal of the second transistor is electrically connected to the second terminal of the third transistor and the first terminal of the fourth transistor; and
the second terminal of the fourth transistor is electrically connected to the light emitting element,

the driving method comprising:
turning off the third transistors and turning on the fifth transistors in a first period; and
turning off the fifth transistors and supplying gradation data to the control terminals of the second transistors by sequentially turning on the third transistors of the plurality of pixel circuit groups while turning on the sixth transistors in a second period after the first period.

8. The driving method according to claim 7 , further comprising, in a third period after the second period:
turning on the first transistors and the fourth transistors while turning off the sixth transistors and the third transistors.

9. The driving method according to claim 8 ,
wherein the third period is an emission period and the light-emitting element emits light.

10. The driving method according to claim 7 ,
wherein the first period is an initialization period.

11. The driving method according to claim 7 ,
wherein the second period is a writing and threshold compensation period.

12. The driving method according to claim 7 ,
wherein the first transistor, the second transistors, the third transistors, the fourth transistors, the fifth transistor, and the sixth transistor are transistors with the same polarity.

13. The display device according to claim 7 ,
wherein the first transistor, the second transistors, the third transistors, the fourth transistors, the fifth transistor, and the sixth transistor are P-channel transistors.

Assignees

• Japan Display Inc

Inventors

• Wu Ilin

Classifications

• G09G2310/0245

  Clearing or presetting the whole screen independently of waveforms, e.g. on power-on (G09G2310/063 takes precedence) · CPC title

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0439

  Pixel structures · CPC title