Memory aggregation device

Patent metadata

Field	Value
Publication number	US-9996489-B2
Application number	US-201514974349-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Jun 19, 2013
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

First claim

What is claimed is:

1. A memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, both the set of input data streams and the set of output data streams being operable to perform one of sending and stop sending new data in each clock cycle, the memory aggregation device comprising:
a set of first-in first-out (FIFO) memories each comprising an input and an output;
an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix;
an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix;
an input selector configured to select the input interconnection matrix according to an input data scheduling scheme;
an output selector configured to select the output interconnection matrix according to an output data scheduling scheme; and
a memory controller coupled to both, the input selector and the output selector, wherein the memory controller is configured to control the input data scheduling scheme such that data from the set of input data streams is spread among the set of FIFO memories in a round-robin manner and to control the output data scheduling scheme such that data from the set of FIFO memories is retrieved to the set of output data streams in a round-robin manner;
wherein the input selector s further configured to receive a set of requests, limit a rate of the set of requests to provide a rate-limited set of requests, provide a lookup vector prepared set of requests based on the rate-limited set of requests and a selection mask, and provide a set of first grants based on the lookup vector prepared set of requests, wherein the selection mask is provided based on a set of second grants.

2. The memory aggregation device of claim 1 , wherein a number of the FIFO memories corresponds to a number of the input data streams.

3. The memory aggregation device of claim 1 , wherein:
the input interconnector comprises a set of multiplexers for implementing the input interconnection matrix; and
the output interconnector comprises a set of multiplexers for implementing the output interconnection matrix.

4. The memory aggregation device of claim 3 , wherein:
the input selector comprises a gate-tree-arbiter logic configured for controlling the set of multiplexers of the input interconnector; and
the output selector comprises a gate-tree-arbiter logic configured for controlling the set of multiplexers of the output interconnector.

5. The memory aggregation device of claim 1 , wherein the input selector is configured to select the input interconnection matrix such that only data streams of the set of input data streams having valid data requests are interconnected to the set of FIFO memories.

6. A memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, both the set of input data streams and the set of output data streams being operable to perform one of sending and stop sending new data in each clock cycle, the memory aggregation device comprising:
a set of first-in first-out (FIFO) memories each comprising an input and an output;
an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix;
an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix;
an input selector configured to select the input interconnection matrix such that data streams of the set of input data streams having valid data requests are compressed to a continuous set of data requests in the set of FIFO memories;
an output selector configured to select the output interconnection matrix according to an output data scheduling scheme; and
a memory controller coupled to both, the input selector and the output selector;
wherein the input selector is further configured to receive a set of requests, limit a rate of the set of requests to provide a rate-limited set of requests, provide a lookup vector prepared set of requests based on the rate-limited set of requests and a selection mask, and provide a set of first grants based on the lookup vector prepared set of requests, wherein the selection mask is provided based on a set of second grants.

7. The memory aggregation device of claim 6 , wherein the input selector is configured to select the input interconnection matrix such that the data streams of the set of input data streams having valid data requests are aligned with a FIFO pointer pointing to a vacant entry in the set of FIFO memories.

8. The memory aggregation device of claim 6 , comprising:
a clock input for receiving a clock signal, wherein the input selector is configured to switch the input interconnection matrix in each clock cycle of the clock signal; and
wherein the output selector is configured to switch the output interconnection matrix in each clock cycle of the clock signal.

9. The memory aggregation device of claim 8 , wherein the input selector is configured to receive an R-bit vector indicating a number of data streams of the set of input data streams having valid data requests and configured to select the input interconnection matrix such that in each clock cycle of the clock signal the first G data requests of the data streams of the set of input data streams are interconnected to the set of FIFO memories, wherein R and G are integer numbers.

10. The memory aggregation device of claim 8 , wherein the output selector is configured to receive an R-bit vector indicating a number of data streams of the set of output data streams having valid data requests and configured to select the output interconnection matrix such that in each clock cycle of the clock signal the first G data requests of the data streams of the set of output data streams are interconnected to the set of FIFO memories, wherein R and G are integer numbers.

11. The memory aggregation device of claim 9 , wherein the memory controller is configured to control R and G depending on a number of vacant entries in the set of FIFO memories.

12. A method for storing a set of input data streams in a set of first-in first-out (FIFO) memories and retrieving data from the set of FIFO memories to a set of output data streams, both the set of input data streams and the set of output data streams being operable to perform one of sending and stop sending new data in each clock cycle, the method comprising:
interconnecting each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix;
interconnecting each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix;
selecting the input interconnection matrix according to an input data scheduling scheme;
selecting the output interconnection matrix according to an output data scheduling scheme;
controlling the input data scheduling scheme such that data from the set of input data streams is spread among the set of FIFO memories in a round-robin manner and controlling the output data scheduling scheme such that data from the set of FIFO memories is retrieved to the set of output data streams in a round-robin manner;
receiving a set of requests;
limiting a rate of the set of requests to provide a rate-limited set of requests;
providing a lookup vector prepared set

Assignees

• Huawei Tech Co Ltd

Inventors

• Shachar Yaron
• Peleg Yoav
• Tal Alex
• Umansky Alex
• Zemach Rami
• Xiong Lixia
• Lu Yuchun

Classifications

• G06F13/4234

  being a memory bus · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/37 Primary

  using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing · CPC title

• G06F5/065

  Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's · CPC title