Resolving page faults out of context for shared contexts

Patent metadata

Field	Value
Publication number	US-9996357-B2
Application number	US-201514928590-A
Country	US
Kind code	B2
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.

First claim

What is claimed is:

1. A method comprising:
creating, by an operating system (OS) kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction;
creating a hidden thread handler in the OS kernel;
accessing, by the hidden thread handler executing on the processor, the temporary effective address to recreate the page fault on the processor; and
resolving the page fault by the OS executing on the processor.

2. The method of claim 1 , wherein the page fault is generated by the coherent accelerator while executing an instruction of a first process, wherein the first process is associated with a first hardware context of the coherent accelerator shared by a plurality of processes including the first process.

3. The method of claim 2 , wherein the VSID is specified in a segment table shared by the plurality of processes sharing the first hardware context, wherein each of the plurality of processes maintains a distinct effective address space.

4. The method of claim 1 , further comprising:
determining a byte offset from the temporary effective address; and
determining a real address of a memory location subject to the page fault using the VSID and the byte offset.

5. The method of claim 1 , wherein creating the temporary effective address includes associating the VSID with a temporary process and makes the VSID addressable by the kernel.

6. The method of claim 1 , wherein the page fault was generated by a first process, wherein the OS kernel, when creating the temporary address, is executing a second process, wherein the first and second processes are unrelated, wherein recreating the page fault on the processor converts the asynchronous interrupt to a synchronous exception.

7. The method of claim 1 , wherein the processor is of a plurality of processors in a system, the method further comprising:
upon determining the page fault was resolved by the operating system, restarting the coherent accelerator.

8. A system, comprising:
a processor;
a coherent accelerator; and
a memory storing program code, which, when executed on the processor, performs an operation comprising:
creating, by an operating system (OS) kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction;
creating a hidden thread handler in the OS kernel;
accessing, by the hidden thread handler executing on the processor, the temporary effective address to recreate the page fault on the processor; and
resolving the page fault by the OS executing on the processor.

9. The system of claim 8 , wherein the page fault is generated by the coherent accelerator while executing an instruction of a first process, wherein the first process is associated with a first hardware context of the coherent accelerator shared by a plurality of processes including the first process.

10. The system of claim 9 , wherein the VSID is specified in a segment table shared by the plurality of processes sharing the first hardware context, wherein each of the plurality of processes maintains a distinct effective address space.

11. The system of claim 8 , further comprising:
determining a byte offset from the temporary effective address; and
determining a real address of a memory location subject to the page fault using the VSID and the byte offset.

12. The system of claim 8 , wherein the page fault was generated by a first process, wherein the OS kernel, when creating the temporary address, is executing a second process, wherein the first and second processes are unrelated wherein recreating the page fault on the processor converts the asynchronous interrupt to a synchronous exception.

13. The system of claim 8 , wherein the processor is of a plurality of processors in a system, the operation further comprising:
upon determining the page fault was resolved by the operating system, restarting the coherent accelerator.

14. A computer program product comprising:
a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:
creating, by an operating system (OS) kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction;
creating a hidden thread handler in the OS kernel;
accessing, by the hidden thread handler executing on the processor, the temporary effective address to recreate the page fault on the processor; and
resolving the page fault by the OS executing on the processor.

15. The computer program product of claim 14 , wherein the page fault is generated by the coherent accelerator while executing an instruction of a first process, wherein the first process is associated with a first hardware context of the coherent accelerator shared by a plurality of processes including the first process.

16. The computer program product of claim 15 , wherein the VSID is specified in a segment table shared by the plurality of processes sharing the first hardware context, wherein each of the plurality of processes maintains a distinct effective address space.

17. The computer program product of claim 14 , further comprising:
determining a byte offset from the temporary effective address; and
determining a real address of a memory location subject to the page fault using the VSID and the byte offset.

18. The computer program product of claim 14 , wherein the page fault was generated by a first process, wherein the OS kernel, when creating the temporary address, is executing a second process, wherein the first and second processes are unrelated, wherein recreating the page fault on the processor converts the asynchronous interrupt to a synchronous exception.

19. The computer program product of claim 14 , wherein the processor is of a plurality of processors in the system, the operation further comprising:
upon determining the page fault was resolved by the operating system, restarting the coherent accelerator.

Assignees

• IBM

Inventors

• Albot Andre L
• Aslot Vishal C
• Flores Arnold
• Mealey Bruce
• Rogers Mark D

Classifications

• G06F9/545

  where tasks reside in different layers, e.g. user- and kernel-space · CPC title

• G06F9/38 Primary

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/1024

  Latency reduction · CPC title