Cyclically interleaved XOR array for error recovery

Patent metadata

Field	Value
Publication number	US-9996285-B2
Application number	US-201615346103-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 8, 2016
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.

First claim

What is claimed is:

1. A memory system, comprising:
a host; and
a memory storage connected with the host and including at least two memory dies, each of the at least two memory dies includes at least two planes, wherein the memory storage is constructed with stripes, the stripes include at least a first stripe and a second stripe,
the first stripe including data pages corresponding to the first stripe and a respective first parity page storing a first XOR parity of the first stripe, and
the second stripe including data pages corresponding to the second stripe and a respective second parity page storing a second XOR parity of the second stripe; and
a controller coupled with the memory storage and configured to
store the data pages and respective parity pages over a plurality of memory dies, and
cyclically interleave the data pages corresponding to the first stripe and the data pages corresponding to the second stripe, wherein the same data pages on different planes in each of the memory dies are constructed into different stripes across the planes, and the number of stripes in each stripe group equals to the number of the planes in each of the memory dies, wherein the stripe group includes a number of stripes cyclically interleaved across all the planes in each of the memory dies.

2. The memory system of claim 1 , wherein the data pages are cyclically interleaved such that the first XOR parity is taken over a first group of data pages limited to one data page per plane.

3. The memory system of claim 2 , wherein the data pages are cyclically interleaved such that the second XOR parity is taken over a second group of data pages limited to one data page per plane.

4. The memory system of claim 1 , further comprising an error correcting code (ECC) unit configured to correct multiple errors in more than one plane.

5. The memory system of claim 4 , wherein the ECC unit is further configured to correct multiple errors in a single plane.

6. The memory system of claim 1 , wherein each data page corresponding to the first stripe and the first parity page are stored on different planes.

7. The memory system of claim 6 , wherein each data page corresponding to the second stripe and the second parity page are stored on different planes.

8. A method of operating a memory system including a memory storage and a controller, comprising:
storing data pages and respective parity pages over a plurality of memory dies of the memory storage, wherein the memory storage includes at least two memory dies, each of the at least two memory dies includes at least two planes, wherein the memory storage is constructed with stripes, the stripes include at least a first stripe and a second stripe;
associating data pages and a first parity page with the first stripe of the memory storage;
associating data pages and a second parity page with the second stripe of the memory storage;
cyclically interleaving the first parity page and data pages associated with the first stripe with the second parity page and data pages associated with the second stripe, wherein the same data pages on different planes in each of the memory dies are constructed into different stripes across the planes, and the number of stripes in each stripe group equals to the number of the planes in each of the memory dies, wherein the stripe group includes a number of stripes cyclically interleaved across all the planes in each of the memory dies;
taking a first XOR parity over the first stripe and storing the first XOR parity in the first parity page; and
taking a second XOR parity over the second stripe and storing the second XOR parity in the second parity page.

9. The method of claim 8 , wherein the cyclically interleaving step is performed such that the first parity page and data pages associated with the first stripe are limited to one page per plane.

10. The method of claim 9 , wherein the cyclically interleaving step is performed such that the second parity page and data pages associated with the second stripe are limited to one page per plane.

11. The method of claim 8 , wherein when multiple errors occur in more than one plane, further comprising correcting, with an error correcting code (ECC) unit, the multiple errors with the first XOR parity and the second XOR parity.

12. The method of claim 8 , further comprising storing each data page corresponding to the first stripe and the first parity page on different planes.

13. The method of claim 12 , further comprising storing each data page corresponding to the second stripe and the second parity page on different planes.

14. A memory device, comprising:
a memory storage including at least two memory dies, each of the at least two memory dies includes at least two planes, wherein the memory storage is constructed with stripes, the stripes include at least a first stripe and a second stripe,
the first stripe including data pages corresponding to the first stripe and a respective first parity page configured to store a first XOR parity of the first stripe, and
the second stripe including data pages corresponding to the second stripe and a respective second parity page configured to store a second XOR parity of the second stripe; and
a controller coupled with the memory storage and configured to
store the data pages and respective parity pages being stored over a plurality of memory dies; and
cyclically interleave the data pages corresponding to the first stripe and the data pages corresponding to the second stripe, wherein the same data pages on different planes in each of the memory dies are constructed into different stripes across the planes, and the number of stripes in each stripe group equals to the number of the planes in each of the memory dies, wherein the stripe group includes a number of stripes cyclically interleaved across all the planes in each of the memory dies.

15. The memory device of claim 14 , wherein the data pages are cyclically interleaved such that the first XOR parity is taken over a first group of data pages limited to one data page per plane.

16. The memory device of claim 15 , wherein the data pages are cyclically interleaved such that the second XOR parity is taken over a second group of data pages limited to one data page per plane.

17. The memory device of claim 14 , further comprising an error correcting code (ECC) unit configured to correct multiple errors in more than one plane.

18. The memory device of claim 17 , wherein the ECC unit is further configured to correct multiple errors in a single plane.

19. The memory device of claim 14 , wherein each data page corresponding to the first stripe and the first parity page are stored on different planes.

20. The memory device of claim 19 , wherein each data page corresponding to the second stripe and the second parity page are stored on different planes.

Assignees

• Sk Hynix Inc

Inventors

• Kang Jingyu
• Wang Chung-Li
• Wang Cai
• Zhang Yibo

Classifications

• H03M13/13 Primary

  Linear codes · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title