Bias generator circuit, voltage generator circuit, communications device, and radar device

Patent metadata

Field	Value
Publication number	US-9996099-B2
Application number	US-201715443284-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Aug 28, 2014
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Disclosed herein is a bias generator circuit for generating a desired bias voltage or bias current using a simple configuration. The bias generator circuit includes a voltage generator circuit, a comparator, and a clock gating circuit. The voltage generator circuit increases or decreases its output voltage in accordance with the number of clock cycles of a given clock signal. The comparator compares the output voltage of the voltage generator circuit to a reference voltage. The clock gating circuit receives, as a control signal, output of the comparator and determines, in accordance with the control signal, whether or not to pass the clock signal to the voltage generator circuit. Thus, the output voltage of the voltage generator circuit, i.e., a bias voltage, is set to be close to the reference voltage.

First claim

What is claimed is:

1. A bias generator circuit comprising:
a voltage generator circuit for increasing or decreasing an output voltage thereof in accordance with a number of clock cycles of a given clock signal;
a comparator for comparing the output voltage of the voltage generator circuit to a reference voltage;
a clock generator for generating the clock signal; and
a clock gating circuit for receiving, as a control signal, output of the comparator and controlling, in accordance with the control signal, whether or not to pass the clock signal supplied from the clock generator to the voltage generator circuit, wherein
the output voltage of the voltage generator circuit is output as a bias voltage, and
the voltage generator circuit comprises:
an output terminal for outputting the output voltage;
a resistor bank in which a plurality of resistors are connected together in series and to which a predetermined voltage is applied between both ends thereof;
a plurality of switches, each of which is selectively turned ON or OFF and has one of two terminals thereof connected to an associated resistor node in the resistor bank and another of the two terminals thereof connected to the output terminal; and
a switch selector section for receiving the clock signal and selectively turning ON any one of the plurality of switches according to the number of clock cycles of the clock signal.

2. The bias generator circuit of claim 1 , wherein
the switch selector section comprises:
a first selector for receiving the clock signal, outputting a plurality of first switch select signals, any one of the plurality of first switch select signals having a predetermined first logical value, and shifting the plurality of first switch select signals on either a rising edge or a falling edge of the clock signal;
a second selector for receiving one of the plurality of first switch select signals, outputting a plurality of second switch select signals, any one of the plurality of second select signals having a predetermined second logical value, and shifting the plurality of second switch select signals on either a rising edge or a falling edge of the one of the plurality of first switch select signals; and
a plurality of logic circuits, each of which is provided for an associated one of the plurality of switches, receives any one of the plurality of first switch select signals and any one of the plurality of second switch select signals, and outputs a signal to control ON/OFF states of the associated switch.

3. The bias generator circuit of claim 1 , wherein the switch selector section comprises either a shift register or a counter.

4. The bias generator circuit of claim 1 , wherein
the voltage generator circuit generally increases its output voltage as the number of clock cycles increases, and the output voltage temporarily decreases as the number of clock cycles increases, or
the voltage generator circuit generally decreases its output voltage as the number of clock cycles increases, and the output voltage temporarily increases as the number of clock cycles increases.

5. The bias generator circuit of claim 1 , wherein
the voltage generator circuit comprises:
a digital-to-analog converter for converting a digital signal into an analog signal; and
a counter for counting the number of clock cycles of the clock signal,
wherein output of the counter is supplied to the digital-to-analog converter, and output of the digital-to-analog converter is delivered as the output voltage.

6. The bias generator circuit of claim 5 , wherein the digital-to-analog converter is an R-2R digital-to-analog converter.

7. The bias generator circuit of claim 1 , wherein the clock gating circuit is configured as an AND gate, an OR gate, or a switched inverter circuit.

8. The bias generator circuit of claim 1 , wherein a flip-flop is arranged on a control signal input end of the clock gating circuit.

9. The bias generator circuit of claim 1 , wherein a low-pass filter is provided on a path through which the output voltage of the voltage generator circuit is transmitted to an input terminal of the comparator.

10. The bias generator circuit of claim 1 , wherein the voltage generator circuit comprises a reset signal terminal to which a reset signal for setting an initial value of the output voltage is applied.

11. A communications device comprising the bias generator circuit of claim 1 , wherein the bias voltage is set by the bias generator circuit either when the device is booted or at regular intervals.

12. A radar device comprising the bias generator circuit of claim 1 , wherein the bias voltage is set by the bias generator circuit either when the device is booted or at regular intervals.

13. A bias generator circuit comprising:
a voltage generator circuit for increasing or decreasing an output voltage thereof in accordance with a number of clock cycles of a given clock signal;
a first transistor for generating a reference current;
a second transistor for receiving the output voltage of the voltage generator circuit at the second transistor's gate and the reference current at the second transistor's drain;
a clock generator for generating the clock signal;
a clock gating circuit for receiving, as a control signal, a drain voltage of the second transistor and controlling, in accordance with the control signal, whether or not to pass the clock signal supplied from the clock generator to the voltage generator circuit; and
a third transistor for receiving the output voltage of the voltage generator circuit at the third transistor's gate and outputting a bias current from the third transistor's drain.

14. The bias generator circuit of claim 13 , wherein a cascode transistor is provided for either the first transistor's drain or the second transistor's drain.

15. The bias generator circuit of claim 13 , wherein an amplifier is arranged between the drain of the second transistor and an input terminal of the clock gating circuit.

16. The bias generator circuit of claim 13 , wherein
the voltage generator circuit comprises:
an output terminal for outputting the output voltage;
a resistor bank in which a plurality of resistors are connected together in series and to which a predetermined voltage is applied between both ends thereof;
a plurality of switches, each of which is selectively turned ON or OFF and has one of two terminals thereof connected to an associated resistor node in the resistor bank and another of the two terminals thereof connected to the output terminal; and
a switch selector section for receiving the clock signal and selectively turning ON any one of the plurality of switches according to the number of clock cycles of the clock signal.

17. The bias generator circuit of claim 16 , wherein
the switch selector section comprises:
a first selector for receiving the clock signal, outputting a plurality of first switch select signals, any one of the plurality of first switch select signals having a predetermined first logical value, and shifting the plurality of first switch select signals on either a rising edge or a falling edge of the clock signal;
a second selector for receiving one of the plurality of first switch select signals, outputting a plurality of second switch select signals, any one of the plurality of second switch select signals having a predetermined second logical value, and shifting the plurality of second switch select signals on either a rising edge or a falling edge of the one of the plurality of first switch select signals; and
a plurality of logic circuits, each of wh

Assignees

• Socionext Inc
• Socionext Inc

Inventors

• Kimura Hiroshi

Classifications

• G05F3/16 Primary

  being semiconductor devices · CPC title

• G05F3/205

  Substrate bias-voltage generators (for static stores G11C5/146) · CPC title

• G05F1/10

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title