Circuit arrangements and a method for receiving information

Patent metadata

Field	Value
Publication number	US-9994179-B2
Application number	US-201213557366-A
Country	US
Kind code	B2
Filing date	Jul 25, 2012
Priority date	Jul 25, 2012
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A circuit arrangement is provided, the circuit arrangement including a receiver configured to receive signal information from a sensor circuit; a discharge circuit configured to discharge a capacitance by providing a discharge pulse; and a modulation circuit configured to modulate a bit pattern onto the discharge pulse.

First claim

What is claimed is:

1. A circuit arrangement, comprising
a discharge circuit configured to discharge a capacitor at a first node by providing a discharge current;
a modulation circuit coupled to the discharge circuit, the modulation circuit configured to modulate a bit pattern onto the discharge current to produce a bit pattern modulated discharge current; and
a receiver circuit configured to send an indication signal to a sensor circuit via the first node and further configured to receive signal information via a signal current flowing through the first node from the sensor circuit after sending the indication signal, wherein the receiver circuit comprises
a transistor having a current conduction path, a first current conduction path terminal coupled to a first end of the current conduction path, and a second current conduction path terminal coupled to a second end of the current conduction path opposite the first end,
a resistor coupled to the second current conduction path terminal of the transistor, the resistor configured to receive at least a portion of the bit pattern modulated discharge current and at least a portion of the signal current, and
a decoder circuit coupled to the resistor, the decoder circuit configured to decode the bit pattern from the bit pattern modulated discharge current and configured to decode the signal information from the signal current.

2. The circuit arrangement according to claim 1 ,
wherein the receiver circuit is configured to receive signal information comprising a current signal from the sensor circuit.

3. The circuit arrangement according to claim 1 ,
wherein the receiver circuit is configured to receive signal information comprising encoded sensor data information from the sensor circuit.

4. The circuit arrangement according to claim 1 ,
wherein the receiver circuit is configured to send an indication signal to the sensor circuit to indicate that signal information can be sent to the receiver circuit from the sensor circuit.

5. The circuit arrangement according to claim 4 ,
wherein the discharge circuit is configured to provide the discharge current for discharging the capacitor after the circuit arrangement has sent the indication signal to the sensor circuit.

6. The circuit arrangement according to claim 1 ,
wherein the receiver circuit is configured to send an indication signal to the sensor circuit to indicate that signal information comprising encoded sensor data information can be sent to the receiver circuit from the sensor circuit.

7. The circuit arrangement according to claim 1 , wherein the discharge circuit is located in the receiver circuit.

8. The circuit arrangement according to claim 1 ,
wherein the discharge circuit is located in the sensor circuit.

9. The circuit arrangement according to claim 1 , wherein the discharge circuit is configured to provide the discharge current for discharging the capacitor, depending on the signal information received by the receiver circuit.

10. The circuit arrangement according to claim 1 ,
wherein the sensor circuit is configured to send the signal information comprising encoded sensor data information to the receiver circuit after the discharge circuit has discharged the capacitance.

11. The circuit arrangement according to claim 1 ,
wherein the discharge circuit comprises a current-sink.

12. The circuit arrangement according to claim 1 ,
wherein the modulation circuit is configured to generate the bit pattern
wherein the bit pattern comprises an encoded bit pattern.

13. The circuit arrangement according to claim 1 , further comprising
one or more processing circuits, wherein the one or more processing circuits are configured to process at least one of the signal information received from the sensor circuit and the bit pattern modulated onto the discharge current.

14. The circuit arrangement according to claim 13 ,
wherein the one or more processing circuits comprise the decoder circuit, wherein the decoder circuit is configured to decode at least one of the bit pattern modulated discharge current and encoded signal information received from the sensor circuit.

15. The circuit arrangement according to claim 13 ,
wherein the one or more processing circuits comprises a current sensor circuit.

16. The circuit arrangement according to claim 13 , further comprising
a controller circuit connected to the one or more processing circuits, wherein the controller circuit is configured to receive at least one of the signal information processed by the one or more processing circuits and the bit pattern modulated discharge current processed by the one or more processing circuits.

17. The circuit arrangement according to claim 16 , wherein the controller circuit is further configured to determine a performance of the circuit arrangement based on the bit pattern modulated discharge current processed by the one or more processing circuits.

18. The circuit arrangement according to claim 1 , further comprising a controller circuit connected to the receiver circuit,
wherein the controller circuit is configured to generate the bit pattern such that it comprises an encoded bit pattern.

19. The circuit arrangement according to claim 18 ,
wherein the controller circuit is configured to control the generation of the discharge current by the discharge circuit.

20. The circuit arrangement according to claim 1 ,
wherein the receiver circuit is configured to generate the bit pattern such that it comprises an encoded bit pattern.

21. The circuit arrangement according to claim 1 ,
wherein the discharge circuit is configured to discharge a capacitance from at least one of the sensor circuit and the receiver circuit.

22. The circuit arrangement of claim 1 , wherein the receiver circuit is further configured to receive the bit pattern modulated discharge current.

23. The circuit arrangement of claim 22 , wherein the circuit arrangement is configured to determine whether the receiver circuit is functioning based on the received bit pattern modulated discharge current.

24. The circuit arrangement of claim 1 , wherein:
the transistor is configured to apply a power supply voltage to the first node; and
the receiver circuit is configured to send the indication signal by modifying the applied power supply voltage.

25. A method for receiving information, the method comprising
providing a discharge current, by a discharge circuit, for discharging a capacitor at a first node;
modulating, by a modulation circuit coupled to the discharge circuit, a bit pattern onto the discharge current to produce a bit pattern modulated discharge current;
sending, by a receiver circuit, an indication signal to a sensor circuit via the first node;
receiving, by the receiver circuit, signal information from the sensor circuit via a signal current flowing through the first node after sending the indication signal;
receiving, by the receiver, the bit pattern modulated discharge current;
decoding the bit pattern from the bit pattern modulated discharge current using a decoder circuit;
determining whether the receiver is functioning based on the decoded bit pattern;
decoding the signal information from the signal current using the decoder circuit; and
generating a power supply voltage at the first node, wherein sending the indication signal comprises modifying the power supply voltage.

26. A circuit arrange

Assignees

• Hammerschmidt Dirk
• Dittfeld Timo
• Infineon Technologies Austria Ag

Inventors

• Hammerschmidt Dirk
• Dittfeld Timo

Classifications

• B60R21/0173 Primary

  Diagnostic or recording means therefor · CPC title