Semiconductor packages with heat dissipation layers and pillars and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9991245-B2
Application number	US-201514958928-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Jan 8, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A semiconductor package comprising: a semiconductor chip; a connection pillar that is disposed adjacent to the semiconductor chip; a first heat dissipation layer disposed on the semiconductor chip; and a second heat dissipation layer disposed on the first heat dissipation layer, the second heat dissipation layer including a first protrusion extending beyond a perimeter of the semiconductor chip and extending towards the connection pillar.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor chip;
a connection pillar that is disposed adjacent to the semiconductor chip in plan view;
a first heat dissipation layer disposed on the semiconductor chip; and
a second heat dissipation layer disposed on the first heat dissipation layer,
the second heat dissipation layer including a body and a first protrusion,
the first protrusion being disposed adjacent to the connection pillar, projecting toward the connection pillar from one of sidewalls of the body, and being separate from the connection pillar,
wherein the first heat dissipation layer is disposed between the semiconductor chip and the second heat dissipation layer, and
wherein the second heat dissipation layer comprises a top surface having substantially the same level as a top surface of the connection pillar.

2. The semiconductor package of claim 1 , further comprising a molding layer encapsulating the semiconductor chip.

3. The semiconductor package of claim 1 ,
wherein the first protrusion extends beyond a perimeter of the semiconductor chip.

4. The semiconductor package of claim 1 , wherein the second heat dissipation layer has an area greater than that of the semiconductor chip in a plan view.

5. The semiconductor package of claim 1 , wherein the connection pillar comprises:
a vertical pillar section; and
a second protrusion extending horizontally from a sidewall of the vertical pillar section toward the first protrusion of the second heat dissipation layer.

6. The semiconductor package of claim 5 , wherein the first and second protrusions are disposed at substantially the same level.

7. The semiconductor package of claim 5 , wherein the first and second protrusions have substantially the same thickness.

8. The semiconductor package of claim 1 , wherein:
in plan view, the first protrusion projects in a first direction from the one of the sidewalls of the body and has a first width in a second direction perpendicular to the first direction and parallel to the semiconductor chip,
in plan view, the connection pillar has a second width in the second direction, and
the first width is substantially the same as the second width.

9. The semiconductor package of claim 1 , further comprising:
a redistribution pattern including a chip region and an interconnection region surrounding the chip region; and
a molding layer;
wherein:
the semiconductor chip is disposed on the chip region and is electrically connected to the redistribution pattern;
the connection pillar is disposed on the interconnection region and is electrically connected to the redistribution pattern; and
the molding layer encapsulates the redistribution pattern and the semiconductor chip.

10. The semiconductor package of claim 1 , further comprising a molding layer encapsulating the semiconductor chip, wherein the molding layer is not disposed between the first protrusion and the connection pillar.

Assignees

• Kim Jae Choon
• Kim Donghan
• Song Jikho
• Umemoto Mitsuo
• Choi Inho
• Samsung Electronics Co Ltd

Inventors

• Kim Jae Choon
• Kim Donghan
• Song Jikho
• Umemoto Mitsuo
• Choi Inho

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title