Guard structure for signal isolation

Patent metadata

Field	Value
Publication number	US-9991209-B2
Application number	US-201415034679-A
Country	US
Kind code	B2
Filing date	Oct 7, 2014
Priority date	Nov 6, 2013
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting surface comprising a first area for hosting at least one electronic component. The method further comprises synthesizing a plurality of thread-like structures over the substrate to collectively form one or more electrically conductive projections extending transverse to the mounting surface. The one or more electrically conductive projections include one or more wall-like structures which are elongate parallel to the mounting surface. The electrically conductive projections can be transferred to another surface such as a major surface of a second substrate. There are further provided a support structure and a guard structure having the wall-like electrically conductive projections which are electrically grounded when in use to provide signal isolation.

First claim

The invention claimed is:

1. An electrical guard structure for providing signal isolation comprising:
a substrate having a mounting surface comprising a first area for hosting at least one electronic component; and
one or more electrically conductive projections implemented onto the substrate, the one or more electrically conductive projections extending transverse to the mounting surface of the substrate;
wherein the one or more electrically conductive projections are formed by collections of a plurality of thread-like structures, the thread-like structures collectively defining the one or more electrically conductive projections extending transverse to the mounting surface;
wherein the one or more electrically conductive projections include one or more wall-like structures;
wherein the one or more wall-like structures are elongate parallel to the mounting surface;
wherein the one or more electrically conductive projections have an aspect ratio of at least 2;
wherein the mounting surface has one or more electrically conductive portions and the thread-like structures are provided on the one or more electrically conductive portions;
wherein the one or more electrically conductive projections are coupled to a ground plane on a surface of the substrate opposite to the mounting surface by providing a plurality of vias extending through the substrate; and
wherein ends of the thread-like structures distal to the mounting surface define a surface of the one or more wall-like structures, the electrical guard structure further comprising an electrically conductive layer on the surface of the one or more wall-like structures.

2. The electrical guard structure according to claim 1 , wherein the diameter of the thread-like structures ranges from 0.01 nanometer to 500 nanometers.

3. The electrical guard structure according to claim 1 , wherein the one or more electrically conductive portions are formed by a layer of electrically conductive material selectively provided on a portion of the mounting surface of the substrate.

4. The electrical guard structure according to claim 1 , wherein the one or more electrically conductive projections are positioned over the vias.

5. The electrical guard structure according to claim 1 , wherein the thread-like structures comprise nanowires, nanofibers or nanotubes.

6. The electrical guard structure according to claim 1 , wherein at least one of the electrically conductive portions has at least 80% of its area being covered by the electrically conductive projections.

7. The electrical guard structure according to claim 1 , wherein the electrically conductive projections extend away from the mounting surface by a distance further than the distance that the at least one electronic component extends away from the mounting surface when the at least one electronic component is hosted on the first area.

8. The electrical guard structure according to claim 1 , wherein the one or more electrically conductive projections are positioned surrounding the first area.

9. The electrical guard structure according to claim 1 , wherein the mounting surface comprises a second area for hosting a second electronic component, at least some of the one or more electrically conductive projections being positioned between the first and second areas.

10. The electrical guard structure according to claim 1 , wherein the one or more electrically conductive projections are arranged to define a channelled space and to restrict signal distribution to the channelled space.

11. The electrical guard structure according to claim 1 , wherein the plurality of thread-like structures comprise carbon nanotubes (CNTs).

12. The electrical guard structure according to claim 11 , wherein the CNTs are single-walled.

13. The electrical guard structure according to claim 1 , wherein the one or more electrically conductive projections have an aspect ratio of at least 3.

14. The electrical guard structure according to claim 13 , wherein the one or more electrically conductive projections have an aspect ratio of at least 5.

15. The electrical guard structure according to claim 1 , wherein each of the wall-like structures has a length in a lengthwise direction and a thickness perpendicular to the lengthwise direction; wherein the ratio of the length and thickness is greater than 2.

16. The electrical guard structure according to claim 15 , wherein each of the wall-like structures extends transversely from the mounting surface by a predefined height, the ratio of the height and the thickness being greater than 2.

17. The electrical guard structure according to claim 15 , wherein the ratio of the length and thickness is greater than 2.5.

18. The electrical guard structure according to claim 17 , wherein the ratio of the length and thickness is greater than 3.

19. The electrical guard structure according to claim 18 , wherein the ratio of the length and thickness is greater than 4.

Assignees

• Thales Solutions Asia Pte Ltd
• Cnrs—Centre National De La Recherche Scient Epst
• Univ Nanyang Tech

Inventors

• Tan Dunlin
• Yu Jong Jen
• Hee David
• Tay Beng Kang
• Baillargeat Dominique

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/735

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title