Display device and driving method thereof

US9990881B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9990881-B2
Application numberUS-201615083874-A
CountryUS
Kind codeB2
Filing dateMar 29, 2016
Priority dateApr 2, 2015
Publication dateJun 5, 2018
Grant dateJun 5, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of driving a display device includes the following steps: a step of applying a first voltage to a drain of the driving transistor from the first power supply line, while applying an initialization voltage lower than the first voltage to a gate of the driving transistor; a step of applying a voltage higher than the initialization voltage lower than the first voltage to the drain of the driving transistor, and applying a voltage based on a video signal to the gate of the driving transistor; and a step of applying the first voltage to a drain of the driving transistor from the first power supply line and supplying a current to the light emitting element while holding the voltage based on the video signal to the gate of the driving transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of driving a display device, the display device includes a plurality of pixels, each of the plurality of pixels includes a light emitting element arranged between a first power supply line applied with a first voltage and a second power supply line applied with a second voltage lower than the first voltage, a driving transistor arranged between the light emitting element and the first power supply line, a source of the driving transistor is electrically connected to the light emitting element, a first switch controlling an electrical connection between a gate of the driving transistor and a signal line supplied with a video signal and an initialization voltage, a second switch controlling an electrical connection between the first power supply line and a drain of the driving transistor, the drain of the drive transistor is connected to a first reset switch and a second reset switch in parallel, wherein the first reset switch controlling an applying of a first reset voltage to the drain of the drive transistor, and the second reset switch controlling an applying of a second reset voltage to the drain of the drive transistor, the method of driving the display device includes the following steps: a step of switching the first switch and the second switch to OFF, and the first reset switch to ON in a source initialization period and applying the first reset voltage to the drain of the driving transistor; a step of switching the first switch to ON and the second switch to OFF in a gate initialization period following the source initialization period, and applying an initialization voltage higher than the first reset voltage to the gate of the driving transistor from the signal line; a step of switching the first switch and the second switch to ON in an offset cancel period following the gate initialization period, applying the initialization voltage to the gate of the driving transistor, supplying a current to the driving transistor from the first power supply line and shifting a source voltage to a high voltage side; a step of switching the first switch to ON, the second switch to OFF and the second reset switch to ON in a video signal writing period following the offset cancel period, applying the video signal to the gate of the driving transistor, and applying the second reset voltage higher than the first reset voltage and lower than the first voltage to the drain of the driving transistor; and a step of switching the first switch to OFF and the second switch to ON in an emission period following the video signal writing period, and supplying a current from the first power supply line to the light emitting element according to a gate voltage of the driving transistor, wherein at least a part of the offset cancel period has a period in which both of the first reset switch and the second reset switch are OFF. 2. The method of driving a display device according to claim 1 , wherein the offset cancel period includes a first offset cancel period and a second offset cancel period, both of the first reset switch and the second reset switch are OFF in the first offset cancel period, and the second reset switch is turned ON and the second reset voltage is applied to the drain of the drive transistor in the second offset cancel period. 3. The method of driving a display device according to claim 1 , wherein the plurality of pixels are arranged in a row direction and a column direction, and an operation in the source initialization period, an operation in the gate initialization period and an operation in the offset cancel period are performed simultaneously on two adjacent rows. 4. A display device comprising a plurality of pixels and a driving circuit, each of the plurality of pixels includes: a first power supply line applied with a first voltage; a light emitting element arranged between the first power supply line applied with the first voltage and a second power supply line applied with a second voltage lower than the first voltage; a driving transistor arranged between the light emitting element and the first power supply line, a source of the driving transistor is electrically connected to the light emitting element; a first switch controlling an electrical connection between a signal line supplied with a video signal and an initialization voltage, and a gate of the driving transistor; a second switch controlling an electrical connection between the first power supply line and a drain of the driving transistor; the driving circuit includes: a first reset switch controlling an applying of a first reset voltage to the drain of the drive transistor; and a second reset switch controlling an applying of a second reset voltage to the drain of the drive transistor, wherein the driving circuit controlling an ON/OFF operation of the first switch, the second switch, the first reset switch and the second reset switch, applying a video signal and an initialization voltage to the signal line, and applying a first reset voltage and a second voltage to the driving transistor, the driving circuit is configured to control the following steps of: a source initialization period for switching the first switch and the second switch to OFF, the first rest switch to ON and applying the first reset voltage to a drain of the driving transistor; a gate initialization period following the source initialization period for switching the first switch to ON and the second switch to OFF, and applying an initialization voltage higher than the first reset voltage to a gate of the driving transistor from the signal line; an offset cancel period following the gate initialization period for switching the first switch and the second switch to ON, applying the initialization voltage to the gate of the driving transistor, supplying a current to the driving transistor from the first power supply line, and shifting a source voltage to a high voltage side; a video signal writing period following the offset cancel period for switching the first switch ON, and the second switch to OFF, and the second reset switch to ON, applying the video signal to the gate of the driving transistor, and applying the second reset voltage higher than the first reset voltage and lower than a voltage of the first power supply line to the drain of the driving transistor; and an emission period following the video signal writing period for switching the first switch to OFF and the second switch to ON, and supplying a current from the first power supply line to the light emitting element according to a gate voltage of the driving transistor, wherein at least a part of the offset cancel period has a period which both of the first reset switch and the second reset switch are OFF. 5. The display device according to claim 4 , wherein the offset cancel period includes a first offset cancel period and a second offset cancel period, both of the first reset switch and the second reset switch are OFF in the first offset cancel period, and the second reset switch is turned ON and the second reset voltage is applied to the drain of the drive transistor in the second offset cancel period. 6. The display device according to claim 5 , wherein the plurality of pixels are arranged in a row direction and a column direction, and the source initialization period, the gate initialization period, the first offset cancel period and the second offset cancel period are performed simultaneously on two adjacent rows. 7. The display device according to claim 4 , wherein the plurality of pixels are arranged in a row direction and a column direction, and the source initialization period, the gate initialization period, the offset cancel period is performed simultaneously on two adjacent rows.

Assignees

Inventors

Classifications

  • Control of polarity reversal in general, other than for liquid crystal displays · CPC title

  • Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines · CPC title

  • Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

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What does patent US9990881B2 cover?
A method of driving a display device includes the following steps: a step of applying a first voltage to a drain of the driving transistor from the first power supply line, while applying an initialization voltage lower than the first voltage to a gate of the driving transistor; a step of applying a voltage higher than the initialization voltage lower than the first voltage to the drain of the …
Who is the assignee on this patent?
Japan Display Inc
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 05 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).