System and method for direct memory access in a flash storage

Patent metadata

Field	Value
Publication number	US-9990315-B2
Application number	US-201615156267-A
Country	US
Kind code	B2
Filing date	May 16, 2016
Priority date	Jul 23, 2009
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A flash storage device provides direct memory access based on a first communication protocol. A host selects the first communication protocol and provides a request to the flash storage device for a direct memory access. Additionally, the host provides data blocks to the flash storage device for the direct memory access. In the first communication protocol, the host need not provide an address to the flash storage device for the direct memory access. The flash storage device stores the data blocks at sequential addresses starting at a predetermined address in the flash storage device. Another host may then select a second communication protocol and transfer the data blocks in the flash storage by using the second communication protocol.

First claim

What is claimed is:

1. A system, comprising:
flash storage;
an interface configured to process requests between a host and the flash storage, the interface comprising a first protocol controller associated with a first communication protocol and a second protocol controller associated with a second communication protocol different than the first communication protocol; and
a controller coupled to the flash storage and the interface, the controller configured to:
perform a direct memory access operation to transfer data between the host and the flash storage through the first protocol controller using the first communication protocol when a select signal from the host indicates the first communication protocol; and
transfer the data between the host and the flash storage through the second protocol controller when the select signal indicates the second communication protocol, wherein the interface is further configured to:
process a request signal from the host, the request signal indicating a request for the direct memory access operation;
provide, in response to the request signal, a notification signal to the controller, the notification signal indicating that the interface received the request from the host;
receive a response signal from the controller, the response signal indicating that the controller is ready to transfer data for the request;
send a ready signal to the host based on the received response signal; and
receive an acknowledgment signal from the host based on the sent ready signal, and
wherein the direct memory access operation is performed subsequent to the receiving the acknowledgment signal.

2. The system of claim 1 , wherein the controller performs the direct memory access operation at a starting predetermined address in the flash storage independent of the host providing an address of the flash storage for the direct memory access operation.

3. The system of claim 1 , further comprising:
a memory coupled to the controller, the memory storing a plurality of predetermined addresses of the flash storage, wherein the controller is configured to:
obtain at least one predetermined address from the plurality of predetermined addresses stored in the memory;
determine whether the direct memory access operation is a read or write operation;
transfer the data from the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a read operation; and
transfer the data to the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a write operation.

4. The system of claim 1 , wherein the request signal is processed by the first protocol controller when the select signal indicates the first communication protocol.

5. The system of claim 1 , wherein the request signal is processed by the second protocol controller when the select signal indicates the second communication protocol.

6. The system of claim 1 , wherein the controller writes the data into the flash storage in the direct memory access operation when the select signal indicates the first communication protocol.

7. The system of claim 6 , wherein the interface is configured to:
receive a write signal over a control bus to the host;
receive, subsequent to receiving the write signal, a first data block of a sequence of data blocks from the host, the write signal being asserted at start of the first data block; and
provide the first data block to the controller, the write signal being deasserted by the host according to the first communication protocol.

8. The system of claim 7 , wherein the first communication protocol specifies a minimum time between assertion and deassertion of the write signal.

9. The system of claim 1 , wherein the controller reads the data from the flash storage in the direct memory access operation when the select signal indicates the second communication protocol.

10. The system of claim 9 , wherein the interface is configured to:
receive a first data block of a sequence of data blocks from the controller;
assert a read signal over a control bus to the host;
send the first data block to the host, the read signal being asserted at start of the first data block; and
deassert the read signal according to the second communication protocol.

11. The system of claim 10 , wherein the second communication protocol specifies a minimum time between assertion and deassertion of the read signal.

12. A computer-implemented method, comprising:
receiving a request from a host for transferring data between the host and flash storage, the request comprising a select signal indicating selection of a first communication protocol or a second communication protocol different than the first communication protocol;
processing a request signal from the host, the request signal indicating a request for the direct memory access operation;
providing, in response to the request signal, a notification signal to the controller, the notification signal indicating that the interface received the request from the host;
receiving a response signal from the controller, the response signal indicating that the controller is ready to transfer data for the request;
sending a ready signal to the host based on the received response signal; and
receiving an acknowledgment signal from the host based on the sent ready signal,
the direct memory access operation being performed subsequent to receiving the acknowledgment signal;
performing a direct memory access operation to transfer data between the host and the flash storage through a first protocol controller using the first communication protocol when the select signal indicates the first communication protocol; and
transferring the data between the host and the flash storage through a second protocol controller when the select signal indicates the second communication protocol.

13. The computer-implemented method of claim 12 , wherein performing the direct memory access operation comprises performing the direct memory access operation at a starting address in the flash storage independent of the host providing an address of the flash storage for the direct memory access operation.

14. The computer-implemented method of claim 12 , further comprising:
obtaining at least one predetermined address stored in a memory;
determining whether the direct memory access operation is a read or write operation;
transferring the data from the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a read operation; and
transferring the data to the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a write operation.

15. The computer-implemented method of claim 12 , wherein the request signal is processed by the first protocol controller when the select signal indicates the first communication protocol.

16. The computer-implemented method of claim 12 , wherein the request signal is processed by the second protocol controller when the select signal indicates the second communication protocol.

17. The computer-implemented method of claim 12 , wherein:
the controller writes the data into the flash storage in the direct memory access operation according to a write signal when the select signal indicates the first communication protocol, and
the first communication protocol specifies a minimum time between assertion and deassertion of the write signal

Assignees

• Hgst Tech Santa Ana Inc
• Western Digital Tech Inc

Inventors

• Moshayedi Mark
• Sadr Seyed Jalal

Classifications

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/1668

  Details of memory controller · CPC title