Split packet transmission DMA engine

Patent metadata

Field	Value
Publication number	US-9990307-B1
Application number	US-201414527642-A
Country	US
Kind code	B1
Filing date	Oct 29, 2014
Priority date	Oct 29, 2014
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

Packet information is stored in split fashion such that a first part is stored in a first device and a second part is stored in a second device. A split packet transmission DMA engine receives an egress packet descriptor. The descriptor does not indicate where the second part is stored but contains information about the first part. Using this information, the DMA engine causes a part of the first part to be transferred from the first device to the DMA engine. Address information in the first part indicates where the second part is stored. The DMA engine uses the address information to cause the second part to be transferred from the second device to the DMA engine. When both the part of the first part and the second part are stored in the DMA engine, then the entire packet is transferred in ordered fashion to an egress device.

First claim

What is claimed is:

1. A system comprising:
a bus;
a first device that is operatively coupled to the bus, wherein the first device includes a memory that stores a first part of packet information, wherein the first part of packet information includes a first descriptor, and wherein the first device can translate a PPI (Packet Portion Identifier) into address information;
a second device that is operatively coupled to the bus, wherein the second device stores a second part of the packet information; and
a third device that is operatively coupled to the bus, wherein the third device comprises:
an egress FIFO (First In First Out) memory; and
means that comprises a buffer memory, wherein the means is for: 1) receiving a second descriptor, wherein the second descriptor includes a PPI and length information, wherein the PPI is not an address and also includes no address; 2) sending the PPI to the first device across the bus such that the first device translates the PPI into first address information and then uses the first address information to read part of the first descriptor from the memory of the first device, 3) receiving the part of the first descriptor from the first device via the bus, 4) extracting second address information from the first descriptor, 5) causing a part of the first part of the packet information to be transferred from the first device to the means across the bus and to be stored into the buffer memory, 6) using the second address information and the length information to cause the second part of the packet information to be transferred from the second device to the means across the bus and to be stored into the buffer memory, wherein the second part of the packet information is transferred in a plurality of bus transfers, and wherein after the transferring of the first part and after the transferring of the second part the first and second parts are stored together in the buffer memory, 7) once the part of the first part and the second part of the packet information have been stored in the buffer memory then transferring the packet information from the buffer memory to the egress FIFO memory, wherein the means comprises no processor that fetches and executes instructions.

2. The system of claim 1 , wherein the first device, the bus, and the second device are parts of an integrated circuit, and wherein the second part of the packet is stored external to the integrated circuit.

3. The system of claim 1 , wherein the part of the first part includes a script code and a packet header but does not include the first descriptor, and wherein the first descriptor is not stored in the buffer memory.

4. The system of claim 1 , wherein after the transferring of the part of the first part and after the transferring of the second part the part of the first part and the second part are stored together in the buffer memory in a single block of contiguous memory locations.

5. The system of claim 1 , wherein the buffer memory comprises a plurality of buffers, and wherein the means is also for: 8) using the length information to allocate a plurality of buffers, wherein all the buffers of the plurality are allocated at the same time, and 9) de-allocating buffers one by one, wherein a buffer is de-allocated by the means upon packet information being transferred from the buffer to the egress FIFO memory.

6. The system of claim 5 , wherein the means is also for: 10) communicating an allocated buffer number across the bus from the third device to the first device such that the first device in return communicates back to the third device across the bus the allocated buffer number and an amount of the first part of packet information.

7. The system of claim 5 , wherein the means is also for: 10) communicating an allocated buffer number across the bus from the third device to the second device such that the second device in return communicates back to the third device across the bus the allocated buffer number and an amount of the second part of packet information.

8. The system of claim 1 , wherein the means is for causing parts of first parts and second parts of multiple different amounts of packet information to be transferred across the bus and to be stored into the buffer memory so that the multiple different amounts of packet information are being assembled in the buffer memory at the same time.

9. The system of claim 1 , wherein a part of a first part of a second amount of packet information is stored in a fourth device, wherein a second part of the second amount of packet information is stored in the second device, and wherein the means of the third device is also for causing the part of the first part and the second part of the second amount of packet information to be transferred across the bus to the third device and to be assembled in the buffer memory.

10. The system of claim 1 , wherein the bus is a Command/Push/Pull (CPP) bus, and wherein the CPP bus comprises a set of command conductors, a set of pull-id conductors, and a set of data conductors.

11. An integrated circuit that is operable with a second memory, wherein the second memory is external to the integrated circuit, wherein the second memory stores a second part of packet information, the integrated circuit comprising:
a bus;
a first memory that stores a first part of the packet information, wherein the first part includes a first descriptor, wherein the first descriptor includes address information; and
a split packet transmission DMA (Direct Memory Access) engine that is operatively coupled to the bus, wherein the DMA engine: 1) receives a second descriptor, wherein the second descriptor includes an identifier associated with the packet information, 2) uses the identifier to obtain a part of the first descriptor from the first memory, 3) extracts the address information from the part of the first descriptor, 4) causes a part of the first part of the packet information to be transferred from the first memory to the DMA engine across the bus and to be stored into a buffer memory in the DMA engine, 5) uses the address information to cause the second part of the packet information to be transferred from the second memory to the DMA engine across the bus and to be stored into the buffer memory, and wherein after the transferring of the part of the first part and after the transferring of the second part the part of the first part and the second part are stored together in the buffer memory, 6) once the part of the first part and the second part of the packet information have been stored in the buffer memory then transfers the packet information from the buffer memory to the egress FIFO memory, wherein the DMA engine comprises no processor that fetches and executes instructions.

12. The integrated circuit of claim 11 , wherein the part of the first part includes a script code and a packet header but does not include the first descriptor.

13. The integrated circuit of claim 11 , wherein the buffer memory comprises a plurality of buffers, and wherein the split packet transmission DMA engine further comprises:
a circuit that maintains a context allocation/de-allocation list; and
a circuit that maintains a buffer allocation/de-allocation list.

14. The integrated circuit of claim 13 , wherein the bus is a Command/Push/Pull (CPP) bus, and wherein the split packet transmission DMA engine further comprises:
a CPP bus interface that is coupled to the bus.

15. The integrated circuit of claim 12 , wherein the second descriptor does not comprise any address.

16. The integrated circuit of claim 12 , wherein the identifier is a PPI (Packet Portion Id

Assignees

• Netronome Systems Inc

Inventors

• Patel Chirag P
• Mirza Salma

Classifications

• G06F13/30 Primary

  with priority control · CPC title

• H04L12/40071

  Packet processing; Packet format (adaptation of digital video signals for transport over a specific network H04N21/2381, H04N21/4363, H04N21/4381; packet switches H04L49/00; intermediate storage or scheduling H04L49/90) · CPC title

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title