Methods for performing a memory resource retry

Patent metadata

Field	Value
Publication number	US-9990294-B2
Application number	US-201615052000-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	Feb 24, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

In an embodiment, an apparatus includes multiple memory resources, and a resource table that includes entries that correspond to respective memory resources of the multiple memory resources. The apparatus also includes a circuit configured to receive a first memory command. The first memory command is associated with a subset of the multiple memory resources. For each memory resource of the subset, the circuit is also configured to set a respective indicator associated with the first memory command, and to store a first value in a first entry of the resource table in response to a determination that the respective memory resource is unavailable. The circuit is also configured to store a second value in each entry of the resource table that corresponds to a memory resource of the subset in response to a determination that an entry corresponding to a given memory resource of the subset includes the first value.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory resources, each memory resource configured to store a particular type of memory command to be processed;
a memory including a global resource table, wherein the global resource table includes a plurality of entries that correspond to respective memory resources of the plurality of memory resources; and
a control circuit configured to:
store a ready indicator in entries of the global resource table indicative of an availability status of those respective memory resources;
receive a first memory command; and
in response to a determination that at least one memory resource utilized by the first memory command is indicated as not ready, set indicators identifying the first memory command in those entries of the global resource table that correspond to the respective memory resources that are utilized by the first memory command.

2. The apparatus of claim 1 , wherein at least one entry of the global resource table that corresponds to a respective memory resource utilized by the first memory command includes an indicator identifying a second memory command waiting for the respective memory resource, wherein the second memory command has an equal or higher priority than other memory commands that are waiting for the respective memory resource to be available.

3. The apparatus of claim 2 , wherein the control circuit is further configured to set a respective indicator to identify the first memory command instead of the second memory command in response to a determination that a priority of the first memory command is greater than the priority of the second memory command.

4. The apparatus of claim 2 , wherein the control circuit is further configured to set a respective indicator to identify the first memory command instead of the second memory command in response to a determination that a priority of the first memory command is the same as the priority of the second memory command and the first memory command is older than the second memory command.

5. The apparatus of claim 2 , wherein the control circuit is further configured to process the first memory command in response to a determination that each of the memory resources utilized by the first memory command is currently available, and that each of those entries of the global resource table that correspond to each of the plurality of memory resources utilized by the first memory command identifies the first memory command.

6. The apparatus of claim 1 , wherein the global resource table includes a respective set of entries corresponding to respective memory resources of the plurality of memory resources, and wherein entries of each respective set corresponds to one of a plurality of priorities.

7. The apparatus of claim 1 , wherein at least one of the plurality of memory resources utilized by the first memory command includes a respective resource queue, and wherein the control circuit is further configured to set a respective local indicator in response to a determination that the first memory command is waiting for the at least one of the plurality of memory resources to have an available entry in the respective resource queue.

8. A method, comprising:
maintaining a global resource table that includes a plurality of entries that correspond to respective memory resources of a plurality of memory resources;
storing a ready indicator in a first entry of the global resource table indicative of an availability status of the respective memory resource;
receiving a first memory command; and
in response to determining that at least one memory resource utilized by the first memory command is indicated as not ready, then, setting indicators identifying the first memory command in those entries of the global resource table that correspond to the respective memory resources that are utilized by the first memory command.

9. The method of claim 8 , wherein at least one entry of the global resource table that corresponds to a respective memory resource utilized by the first memory command includes an indicator identifying a second memory command waiting for the respective memory resource, wherein the second memory command has an equal or higher priority than other memory commands that are waiting for the respective memory resource to be available.

10. The method of claim 9 , further comprising setting a respective indicator identifying the first memory command instead of the second memory command in response to determining that a priority of the first memory command is greater than the priority of the second memory command.

11. The method of claim 9 , further comprising setting a respective indicator identifying the first memory command instead of the second memory command in response to determining that a priority of the first memory command is the same as the priority of the second memory command and the first memory command is older than the second memory command.

12. The method of claim 9 , further comprising processing the first memory command in response to determining that each of the memory resources utilized by the first memory command is currently available, and that each of those entries of the global resource table that correspond to each of the plurality of memory resources utilized by the first memory command identifies the first memory command.

13. The method of claim 8 , wherein the global resource table includes a respective set of entries corresponding to respective memory resources of the plurality of memory resources, and wherein entries of each respective set corresponds to one of a plurality of priorities.

14. The method of claim 8 , wherein at least one of the plurality of memory resources utilized by the first memory command includes a respective resource queue, and further comprising, setting a respective local indicator in response to determining that the first memory command is waiting for the at least one of the plurality of memory resources to have an available entry in the respective resource queue.

15. A system, comprising:
a memory;
at least one processor configured to generate a plurality of memory commands for accessing the memory;
a plurality of memory resources; and
a memory controller circuit configured to:
maintain a global resource table that includes a plurality of entries that correspond to respective memory resources of the plurality of memory resources;
store a ready indicator in entries of the global resource table indicative of an availability status of those respective memory resources;
receive a first memory command of the plurality of memory commands; and
in response to a determination that at least one memory resource utilized by the first memory command is indicated as not ready, set indicators identifying the first memory command in those entries of the global resource table that correspond to the respective memory resources that are utilized by the first memory command.

16. The system of claim 15 , wherein at least one entry of the global resource table that corresponds to a respective memory resource utilized by the first memory command includes an indicator identifying a second memory command of the plurality of memory commands waiting for the respective memory resource, wherein the second memory command has an equal or higher priority than other memory commands of the plurality of memory commands that are waiting for the respective memory resource to be available.

17. The system of claim 16 , wherein the memory controller circuit is further configured to set a respective indicator to identify the first memory

Assignees

• Apple Inc

Inventors

• Saha Bikram
• Kaushikkar Harshavardhan
• Biswas Sukalpa
• Jain Prashant

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0842 Primary

  for multiprocessing or multitasking · CPC title

• G06F2212/283

  Plural cache memories · CPC title