System and method for repurposing dead cache blocks

Patent metadata

Field	Value
Publication number	US-9990289-B2
Application number	US-201414491296-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A processing system having a multilevel cache hierarchy employs techniques for repurposing dead cache blocks so as to use otherwise wasted space in a cache hierarchy employing a write-back scheme. For a cache line containing invalid data with a valid tag, the valid tag is maintained for cache coherence purposes or otherwise, resulting in a valid tag for a dead cache block. A cache controller repurposes the dead cache block by storing any of a variety of new data at the dead cache block, while storing the new tag in a tag entry of a dead block tag way with an identifier indicating the location of the new data.

First claim

What is claimed is:

1. A method comprising:
responsive to invalidation of first data of a cache line of a first cache of a processing system employing a write-back caching policy:
repurposing the cache line to concurrently store, at the cache line, second data and a first tag associated with the first data for a cache coherence scheme of the processing system, wherein the cache line maintains the first tag after storing the second data in the cache line.

2. The method of claim 1 , wherein repurposing the cache line includes associating a second tag with the second data.

3. The method of claim 2 , wherein:
the first cache comprises a cache line array having N ways and a tag array having at least N+1 ways;
the first tag is stored in a first tag entry of a first way of the tag array; and
the second tag is stored in a second tag entry of a second way of the tag array.

4. The method of claim 3 , wherein repurposing the cache line further comprises:
moving the first tag from the second tag entry of the second way to the first tag entry of the first way; and
storing the second tag in the second tag entry of the second way after moving the first tag.

5. The method of claim 3 , wherein:
the cache line comprises a cache line of the first way of the cache line array; and
the second tag comprises an identifier associated with the first way of the cache line array.

6. The method of claim 1 , wherein repurposing the cache line comprises:
prefetching the second data from a memory; and
storing the prefetched second data to the cache line.

7. The method of claim 1 , wherein repurposing the cache line comprises:
storing a duplicate of third data of the first cache as the second data in the cache line.

8. The method of claim 1 , wherein repurposing the cache line comprises:
compressing third data to generate the second data; and
storing the second data in the cache line.

9. The method of claim 1 , wherein repurposing the cache line comprises:
storing the second data in the cache line in response to eviction of the second data from a second cache.

10. The method of claim 1 , further comprising:
invalidating the first data responsive to modification of a cache line of a second cache, the cache line of the second cache corresponding to the cache line of the first cache.

11. A method comprising:
invalidating a first data block of a cache line of a first cache responsive to a modification of the first data block at a second cache, the first data block associated with a first tag of the first cache;
responsive to identifying the first data block as invalid, replacing the first data block in the cache line of the first cache with a second data block; and
associating a second tag in the first cache with the second data block while maintaining the first tag in the cache line of the first cache, wherein the first cache and the second cache maintain a write-back caching policy, and further wherein the cache line of the first cache maintains the first tag after replacing the first data block with the second data block to concurrently store both the first tag and the second data block in the cache line.

12. The method of claim 11 , wherein:
the first tag is stored in a first way of a tag array of the first cache; and
wherein associating the second tag comprises concurrently storing the second tag in a second way of the tag array.

13. The method of claim 11 , wherein the second data block comprises at least one of: prefetched data; compressed data; duplicate data; and data evicted from the second cache.

14. A system comprising:
a cache hierarchy comprising a first cache and a second cache; and
a cache controller to, in response to invalidation of first data at a cache line of the first cache, repurpose the cache line to concurrently store, at the cache line, a second data and a first tag associated with the first data for a cache coherence scheme, wherein the cache line maintains the first tag after storing the second data in the cache line.

15. The system of claim 14 , wherein the cache hierarchy employs a write-back caching policy.

16. The system of claim 14 , wherein the cache controller is to repurpose the cache line at least in part by associating a second tag with the second data.

17. The system of claim 16 , wherein:
the first cache comprises a cache line array having N ways and a tag array having at least N+1 ways;
the first tag is stored in a first tag entry of a first way of the tag array; and
the second tag is stored in a second tag entry of a second way of the tag array.

18. The system of claim 17 , wherein:
the cache line comprises a cache line of the first way of the cache line array; and
the second tag comprises an identifier associated with the first way of the cache line array.

19. The system of claim 14 , wherein the cache controller further is to:
invalidate the first data responsive to modification of a cache line of a second cache, the cache line of the second cache corresponding to the cache line of the first cache.

20. The system of claim 14 , wherein the second data comprises at least one of: prefetched data; compressed data; duplicate data; and data evicted from a second cache.

Assignees

• Advanced Micro Devices Inc

Inventors

• Loh Gabriel H
• Hower Derek R
• Che Shuai

Classifications

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F12/0864

  using pseudo-associative means, e.g. set-associative or hashing · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title