Memory tracking using copy-back cache for 1:1 device redundancy

Patent metadata

Field	Value
Publication number	US-9990286-B1
Application number	US-201715588315-A
Country	US
Kind code	B1
Filing date	May 5, 2017
Priority date	May 5, 2017
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A redundant process controller arrangement includes a primary controller and parallel connected secondary controller each coupled to actuators and sensors coupled to processing equipment. The primary and secondary controllers include a main writable memory including a cache data control algorithm, central processing unit (CPU) with cache memory including cache not supporting write-thru, tracker logic coupled to a control cycle database in a tracked memory region and to a primary tracking buffer. A redundancy link is between the CPUs for passing tracked changes. The algorithm implements memory tracking using copy-back including the primary tracker logic each cycle writing tracked changes into the primary tracking buffer, and at cycle end, transferring tracked changes from the primary tracking buffer to the secondary controller over the redundancy link, and writing tracked changes to the secondary control database.

First claim

The invention claimed is:

1. A method of memory tracking using copy-back, comprising:
providing a redundant process controller arrangement for an industrial control system comprising a primary controller and a parallel connected redundant secondary controller both coupled by input/outputs (IOs) to actuators and sensors coupled to processing equipment, said primary controller including a primary main writable memory including a primary tracked memory region with a primary control cycle database residing therein, a primary tracking buffer and a cache data control algorithm, a primary central processing unit (CPU) with cache memory including a cache not supporting write-thru, and primary tracker logic coupled by a memory controller to said primary control cycle database in said primary tracked memory region and to said primary tracking buffer, said secondary controller including a secondary main writable memory including a secondary tracked memory region with a secondary control cycle database residing therein, a secondary tracking buffer and a secondary cache data control algorithm, a secondary CPU including a cache memory including a cache not supporting write-thru, secondary tracker logic coupled by a memory controller to said secondary control cycle database residing in said secondary tracked memory region and to said secondary tracking buffer, and a redundancy link between said primary CPU and said secondary CPU;
said primary tracker logic writing tracked changes into said primary tracking buffer during each cycle, and
responsive to an end of cycle notification, said algorithm:
transferring said tracked changes from said primary tracking buffer to said secondary controller over said redundancy link, and
writing said tracked changes to said secondary control cycle database.

2. The method of claim 1 , wherein said tracker logic performs cache line reading and writing of said cache memory for said primary main writable memory, and includes registers which define an address range in said primary main writable memory that corresponds to a tracked address range for said tracked changes, a start and end of said primary tracking buffer, and a pointer showing how much of said tracked changes has been written to said primary tracking buffer.

3. The method of claim 1 , further comprising after said end of cycle notification purging said L1 cache of said primary cache memory of all its contents and writing all said tracked changes to said primary control cycle database.

4. The method of claim 1 , wherein said tracker logic resides in a field-programmable gate array (FPGA) and said primary main writable memory and said secondary main writable memory both comprise random access memory (RAM),
wherein said FPGA in said primary controller is programmed to recognize a unique address range through which a primary tracked memory region is accessed, and wherein said primary tracker logic uses said memory controller to access said primary main writable memory at its normal hardware address, and wherein said access to said primary tracked memory region is only permitted through said unique address range.

5. The method of claim 1 , wherein following a command or failure of said primary controller, said secondary controller becomes a backup primary controller and assumes controlling of said processing equipment.

6. The method of claim 1 , further comprising controlling an industrial process using said secondary controller during a fault of said primary controller operating on current data reflecting said tracked changes in a last cycle.

7. The method of claim 1 , wherein said cache memory in said primary and said secondary controller includes a level 1 (L1) cache that does not support write-thru and a L2 cache that supports write-thru.

8. A redundant process controller arrangement for a process control system, comprising:
a primary controller and a parallel connected redundant secondary controller both coupled by input/outputs (IOs) to actuators and sensors coupled to processing equipment;
said primary controller including a primary main writable memory including a primary tracked memory region with a primary control cycle database residing therein, a primary cache data control algorithm, primary central processing unit (CPU) with cache memory including cache that does not support write-thru, primary tracker logic coupled by a primary memory controller to a primary control cycle database residing in a primary tracked memory region and to a primary tracking buffer,
said secondary controller including a secondary main writable memory including a secondary tracked memory region with a secondary control cycle database residing therein, a secondary tracking buffer a secondary cache data control algorithm, secondary CPU including a cache memory including cache not supporting write-thru, secondary tracker logic coupled by a secondary memory controller to a secondary control cycle database residing in a secondary tracked memory region and to a secondary tracking buffer; and a redundancy link between said primary CPU and said secondary CPU for passing tracked changes to said secondary CPU;
said cache data control algorithms for implementing a method of memory tracking using copy-back, comprising:
said primary tracker logic during each cycle writing said tracked changes into said primary tracking buffer, and
responsive to an end of cycle notification, said algorithm:
transferring said tracked changes from said primary tracking buffer to said secondary controller over said redundancy link, and
writing said tracked changes to said secondary control cycle database.

9. The redundant process controller arrangement of claim 8 , wherein said tracker logic is for performing cache line reading and writing of said cache memory for said primary main writable memory, and includes registers which define an address range in said primary main writable memory that corresponds to a tracked address range for said tracked changes, a start and end of said primary tracking buffer, and a pointer showing how much of said tracked changes has been written to said tracking buffer.

10. The redundant process controller arrangement of claim 8 , wherein said algorithm further implements after said end of cycle notification purging said L1 cache of said primary cache memory of all its contents and writing all said tracked changes to said primary control cycle database.

11. The redundant process controller arrangement of claim 8 , wherein said tracker logic resides in a field-programmable gate array (FPGA) and said primary main writable memory and said secondary main writable memory both comprise random access memory (RAM),
and wherein said FPGA in said primary controller is programmed to recognize a unique address range through which said primary tracked memory region is accessed, and wherein said primary tracker logic uses said primary memory controller to access said primary main writable memory at its normal hardware address, and wherein said access to said primary tracked memory region is only permitted through said unique address range.

12. The redundant process controller arrangement of claim 8 , wherein following a command or failure of said primary controller, said algorithm further implements said secondary controller becoming a backup primary controller and assuming controlling of said processing equipment.

13. The redundant process controller arrangement of claim 8 , wherein said cache memory including a level 1 (L1) cache that does not support write-thru and a L2 cache that supports write-thru.

14. The redundant process controller arrangement of claim 11 , wherein said primary and sai

Assignees

• Honeywell Int Inc
• Honeywell Int Inc

Inventors

• Mclaughlin Paul F
• Massey William Russell
• Drayton Gary
• Chernoguzov Alexander

Classifications

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F11/2028

  eliminating a faulty processor or activating a spare · CPC title

• G06F11/2097

  maintaining the standby controller/processing unit updated (initialisation or re-synchronisation thereof G06F11/1658 and subgroups) · CPC title

• G06F12/0806 Primary

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06F2212/283

  Plural cache memories · CPC title