Memory system and wear-leveling method thereof

Patent metadata

Field	Value
Publication number	US-9990153-B2
Application number	US-201715618597-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Oct 24, 2016
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A memory system includes a memory device performing write operations on lines included in a memory block among a plurality of memory blocks included in the memory device; a counting unit counting a write count for each of the plurality of memory blocks, and outputting the write counts; a first wear-leveling unit performing a wear leveling operation by shifting the lines of each of the plurality of memory blocks; and a second wear-leveling unit detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block, wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the lines included in the selected memory block.

First claim

What is claimed is:

1. A memory system comprising:
a memory device configured to perform write operations on one or more lines included in a memory block among a plurality of memory blocks included in the memory device;
a counting unit configured to count a write count for each of the plurality of memory blocks, and output the write counts;
a first wear-leveling unit configured to perform a wear leveling operation by shifting the one or more lines of each of the plurality of memory blocks; and
a second wear-leveling unit configured to detect hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swap the hot memory block with the cold memory block,
wherein the second wear-leveling unit selects at least one memory block among the plurality of memory blocks based on the write counts, and checks whether the write operation is performed on each of the one or more lines included in the selected memory block.

2. The memory system of claim 1 , wherein, on a regular cycle, when the write count of the selected memory block is greater than or equal to a first reference value, and the number of first lines on which the write operation are performed is less than or equal to a second reference value, the second wear-leveling unit detects the first lines as a hot line.

3. The memory system of claim 1 , wherein the second wear-leveling unit generates flag data to check the write operations on the one or more lines and wherein the memory device is a variable resistance memory device.

4. An operating method for a memory system, comprising:
counting the number of write operations for a plurality of memory blocks of a memory device, and output write counts;
performing a first wear-leveling operation by shifting a plurality of lines included in each of the plurality of memory blocks;
performing a second wear-leveling operation by detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory block;
selecting at least one of the plurality of memory blocks based on the write counts, and detecting a hot line by checking whether the write operation is performed on each of the plurality of lines included in the selected memory block.

5. The operating method of claim 4 , wherein, on a regular cycle, when the write count of the selected memory block is greater than or equal to a first reference value, and the number of first lines on which the write operation is performed is less than or equal to a second reference value, the first lines are detected as the hot line.

6. The operating method of claim 5 , further comprising
performing the first wear-leveling operation by shifting the detected hot line.

7. The operating method of claim 5 , further comprising:
selecting a second line on which the write operation is not performed, among the plurality of lines, as a cold line; and
swapping the detected hot line with the selected cold line.

8. The operating method of claim 5 , further comprising:
generating flag data of 1-bit assigned to each of the plurality of lines included in the selected memory block.

9. The operating method of claim 8 , wherein the detecting of the hot line by checking whether the write operation is performed on the plurality of lines comprises:
changing the flag data of a line on which the write operation is performed, among the plurality of lines, from a low level to a high level;
counting the number of flag data changed to the high level; and
comparing the counted number of flag data with the second reference value when the write count of the selected memory block is greater than or equal to the first reference value.

10. The operating method of claim 4 , wherein the selecting of at least one of the plurality of memory blocks comprises:
checking the write counts of the plurality of memory blocks on a regular cycle; and
selecting a predetermined number of memory blocks whose write counts are within a preset upper range, as a check result.

11. The operating method of claim 4 , wherein the selecting of at least one of the plurality of memory blocks comprises:
checking write counts of first memory blocks except for previously-selected memory blocks among the plurality of memory blocks, on a regular cycle;
selecting a second memory block whose write count is greater than or equal to a third reference value, among the first memory blocks, as a check result; and
selecting a predetermined number of memory blocks whose write counts are within a preset upper range, among the second memory block and the previously-selected memory blocks.

12. The operating method of claim 5 , wherein the write operation is performed on a basis of the plurality of lines.

13. The operating method of claim 12 , wherein the first reference value is set based on a maximum count of the write operations allowed to be performed on the plurality of lines, and the second reference value is set based on the number of the lines.

14. An operating method for a memory system, comprising:
counting the number of write operations for a plurality of memory blocks of a variable resistance memory device, and output the write counts;
performing a first wear-leveling operation by shifting a plurality of lines included in each of the plurality of memory blocks;
performing a second wear-leveling operation by detecting hot and cold memory blocks among the plurality of memory blocks based on the write counts, and swapping the hot memory block with the cold memory blocks;
selecting at least one of the plurality of memory blocks based on the write counts, and grouping the plurality of lines included in the selected memory block into a top group, a middle group and a bottom group depending on the number of write operations performed on the plurality of lines; and
detecting, on a regular cycle, a line of the top group as a hot line depending on the number of the grouped lines and the number of the write operations performed on the bottom group, when the write count of the selected memory block is greater than or equal to a first reference value.

15. The operating method of claim 14 , further comprising:
generating flag data of 2-bit assigned to each of the plurality of lines included in the selected memory block.

16. The operating method of claim 15 , wherein the grouping of the plurality of lines comprises:
classifying the plurality of lines into the bottom group, a first middle group, a second middle group, and the top group using first to fourth data of the 2-bit flag data; and
storing the number of write operations performed on the bottom group.

17. The operating method of claim 16 , wherein the classifying of the plurality of lines into the bottom group, the first middle group, the second middle group, and the top group comprises:
classifying, as the bottom group, a line on which the write operation is not performed among the plurality of lines;
classifying, as the first middle group, a line on which the write operation is performed once among lines of the bottom group;
classifying, as the second middle group, a line on which the write operation is performed once more among lines of the first middle group; and
classifying, as the top group, a line on which the write operation is performed at least once more among lines of the second middle group.

18. The operating method of claim 17 , wherein, when all of the lines of the bottom group are classified into the first middle group, the second middle group, or the top group, the grouping of the p

Assignees

• Sk Hynix Inc

Inventors

• Kwon Jung-Hyun
• Kim Dong-Gun
• JO Sang-Gu

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title