Display substrate structure

Patent metadata

Field	Value
Publication number	US-9989821-B2
Application number	US-201514602286-A
Country	US
Kind code	B2
Filing date	Jan 22, 2015
Priority date	Jan 28, 2014
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

A display substrate structure includes a substrate, at least one chip, and a plurality of conductive lines. A display region and a periphery region are defined on the substrate. The periphery region is disposed around the display region, and the chip is disposed in the periphery region. The conductive lines are disposed in the periphery region and at least between the chip and the display region. Each conductive line has a fan-out portion and at least one adjustment portion. Each adjustment portion is electrically connected to the fan-out portion of the same conductive line. The adjustment portion of each conductive line has a winding wire, and at least one of the adjustment portions of the conductive lines has a straight wire, which is electrically connected to and at least partially overlaps the winding wire of the same conductive line.

First claim

What is claimed is:

1. A display substrate structure, comprising:
a substrate, having a display region and a peripheral region defined thereon, the peripheral region being disposed around the display region;
at least one chip, disposed in the peripheral region; and
a plurality of conductive lines, disposed at least in the peripheral region and at least between the chip and the display region, each of the conductive lines including a fan-out portion and at least one adjustment portion electrically connected to the fan-out portion of the same conductive line, the adjustment portion of each of the conductive lines having a winding wire, and at least one of the adjustment portions of the conductive lines further having a straight wire, wherein the straight wire and the winding wire of the same conductive line at least partially overlap each other and are electrically connected to each other.

2. The display substrate structure of claim 1 , wherein at least one of the adjustment portions of the conductive lines do not have the straight wire.

3. The display substrate structure of claim 1 , wherein the adjustment portions of at least two of the conductive lines respectively have straight wires, and at least two of the straight wires of the conductive lines having both the winding wires and the straight wires have different lengths.

4. The display substrate structure of claim 3 , wherein the resistances of the fan-out portions of the conductive lines are not completely the same, and the length of the straight wire of one of the conductive lines whose fan-out portion has relatively high resistance is longer than the length of the straight wire of another one of the conductive lines whose fan-out portion has relatively low resistance.

5. The display substrate structure of claim 4 , wherein the fan-out portions of the conductive lines are arranged as a fan-out shape, and the longer fan-out portion has a greater resistance than the resistance of the shorter fan-out portion.

6. The display substrate structure of claim 3 , wherein the chip has a first datum point and a second datum point, at least some of the conductive lines are arranged from the first datum point to the second datum point in order, wherein the fan-out portion of the conductive line closer to the second datum point has a greater resistance than that of the fan-out portion of the conductive line farther to the second datum point, and the straight wire of the conductive line closer to the second datum point is longer than the straight wire of the conductive line farther to the second datum.

7. The display substrate structure of claim 1 , wherein the straight wires and the winding wires are composed of the same conductive layer.

8. The display substrate structure of claim 1 , wherein the straight wires and the winding wires are composed of different conductive layers.

9. The display substrate structure of claim 8 , further comprising a plurality of contact elements respectively disposed between the straight wire and the winding wire of the same conductive line to electrically connect the straight wire and the winding wire of the same conductive line.

10. The display substrate structure of claim 1 , wherein the winding wires of the conduct wires have completely the same patterns.

11. The display substrate structure of claim 10 , wherein each of the winding wires has a pattern including S shapes or saw-toothed shapes which continuously and evenly arranged.

12. The display substrate structure of claim 1 , wherein the conductive lines substantially extend from the chip to the display region along a direction, the display substrate structure further comprises an alignment layer disposed on the conductive lines, and the alignment layer is formed by rubbing an alignment material on the substrate along the same direction.

13. The display substrate structure of claim 1 , wherein the adjustment portion of each of the conductive lines is disposed between the fan-out portion of the same conductive line and the display region and is connected to the display region.

14. The display substrate structure of claim 1 , wherein each of the conductive lines includes two adjustment portions respectively disposed at two ends of the fan-out portion of the same conductive line.

15. The display substrate structure of claim 1 , wherein the lengths of the winding wires of the adjustment portions are not completely the same.

Assignees

• Au Optronics Corp

Inventors

• Cheng Keng-Chuan
• Fu Chien-Hao
• Lin Chien-Ju

Classifications

• H05K1/0289

  having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes · CPC title

• G02F1/13452 Primary

  Conductors connecting driver circuitry and terminals of panels · CPC title

• G02F1/133784

  by rubbing · CPC title