Front end circuitry with analog sampling and decoding for ultrasound imaging systems and methods of use

Patent metadata

Field	Value
Publication number	US-9989497-B2
Application number	US-54345209-A
Country	US
Kind code	B2
Filing date	Aug 18, 2009
Priority date	Aug 18, 2008
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

Pulse-echo imaging systems and methods are provided, including a transmit code sequencer and a pulse generation circuit, The transmit code sequencer is configured to input a transmit code sequence to the pulse generation circuit. A transducer is configured to receive electrical signals provided as pulses using coded excitation according to the transmit code sequence, and to transduce the electrical signals to pulses of energy other than electrical signals. The transducer is further configured to receive echoes of the pulses of energy other than electrical signals and convert the echoes to received electrical signals generate using coded excitation. A receive circuit is configured to receive the received electrical signals generate using coded excitation, perform analog sampling of the received electrical signals generate using coded excitation, and provide a weighted, summed digital signal by processing the analog samples. At least one example of a pulse imaging system described is configured for ultrasonic pulse-echoes. At least one example of a pulse imaging system described is a medical diagnostic imaging system.

First claim

That which is claimed is:

1. A pulse-echo imaging system comprising:
a pulse generation circuit configured to provide electrical signals representative of a transmit code sequence;
a transducer configured to receive the electrical signals provided by the pulse generation circuit as pulses using coded excitation according to said transmit code sequence, and to transduce said electrical signals to pulses of energy other than electrical signals; said transducer being further configured to receive echoes of said pulses of energy other than electrical signals and convert the echoes to received electrical signals; and
a receive circuit configured to:
receive said received electrical signals;
perform analog sampling of the received electrical signals;
perform analog decoding of the received electrical signals using information about the coded excitation and using an analog decoder circuit; and
provide a weighted, summed digital signal using information obtained from the analog sampling and the analog decoding;

processing circuit configured to;
receive weighted sum digital signal; and
generate image using the digital signal;

display coupled to processing circuit to display the image.

2. The system of claim 1 , wherein said receive circuit weights said analog samples, sums said weighted analog samples and converts a resulting summed, weighted analog signal to a summed, weighted digital signal.

3. The system of claim 1 , wherein said analog decoder circuit comprises a two-level filter.

4. The system of claim 3 wherein said analog decoder circuit further comprises a switch and a summing device;
wherein the received electrical signals are directed down two circuit paths of said two-level filter, wherein scaled samples are produced by one of said two circuit paths analog multiplying the signals by +1 and the other of the two circuit paths analog multiplying the signals by −1, and, depending upon whether a resulting signal coefficient is +1 or −1, said switch selects one of the circuit paths and passes the scaled sample to said summing device; and
wherein said summing device sums the scaled samples received to yield a decoded sample.

5. The system of claim 1 , wherein said receive circuit comprises:
a single-ended circuit implementation having two parallel branches, each containing an analog coefficient multiplier;
one of said branches comprising an inverting unity gain amplifier and the other of said branches comprising a non-inverting unity gain amplifier;
a switch or transmission gate configured to select one of said branches based upon a filter coefficient assigned by said amplifiers;
the selected branch feeding into a single-ended sampling switched-capacitor integrator with reset capability that samples a continuous signal during one phase to provide a sampled signal and adds the sampled signal to previous sampled signals during a subsequent phase.

6. The system of claim 1 , wherein said receive circuit comprises a differential circuit, said differential circuit comprising:
a switching circuit that implements positive and negative coefficients by interchanging positive and negative terminals of differential branches of said differential circuit; and
a differential sampling, switched capacitor integrator with reset capability configured to sample a continuous signal during one phase to provide a sampled signal, and, in a second phase, to add the sampled signal to previous sampled signals.

7. The system of claim 1 , wherein said receive circuit comprises more than two parallel circuit paths, a switching device and a summing device;
wherein the received electrical signals are directed down the more than two circuit paths, wherein scaled samples are produced by said more than two circuit paths, each containing an analog multiplier having a gain set to provide multiple arbitrary filter coefficients where each branch assigns a different filter coefficient, and, depending upon the resulting signal coefficient, said switch device selects one of the circuit paths having a predefined one of the filter coefficients and passes the scaled sample from the selected circuit path to said summing device;
wherein said summing device sums the scaled samples received to yield a decoded sample.

8. The system of claim 1 , wherein said receive circuit comprises:
a single-ended circuit implementation having two parallel branches, each containing an adjustable sampling capacitor;
each said adjustable sampling capacitor being adjustable for multiple different coefficient values configured for decoding coded excitation signals using different codes.

9. The system of claim 1 , wherein said receive circuit comprises a differential circuit, said differential circuit comprising:
a switching circuit capable of implementing more than two different filter coefficients by interchanging positive and negative terminals of differential branches of said differential circuit and by providing each differential branch with an adjustable sampling capacitor that is adjustable for multiple different coefficient values; and
a differential sampling, switched capacitor integrator with reset capability configured to sample a continuous signal during one phase to provide a sampled signal, and, in a second phase, to add the sampled signal to previous sampled signals.

10. The system of claim 1 , wherein said receive circuit comprises:
a plurality of sample and hold circuits, each configured for sampling and holding one sample of the received electrical signals over one code length; and
a switched-capacitor integrator configured to commence integration and integrate said samples after all samples from an entire received pulse have been acquired by said sample and hold circuits.

11. The system of claim 1 , wherein said receive circuit comprises:
an analog memory bank provided for holding each sample of the received electrical signals over one code length; and
a switched-capacitor integrator configured to commence integration and integrate said samples after all samples from an entire received pulse have been held by said analog memory bank.

12. The system of claim 10 , wherein a charge storage capacity of each of said sample and hold circuits is set as a function of a predefined filter coefficient, respectively.

13. The system of claim 11 , wherein said analog memory bank comprises a plurality of memory cells each having a charge storage capacity, wherein said charge storage capacity of each of said memory cells is set as a function of a predefined filter coefficient, respectively.

14. The system of claim 10 , wherein each said sample and hold circuit comprises an adjustable sampling capacitor, each said adjustable sampling capacitor being adjustable for more than two different coefficient values.

15. The system of claim 1 , wherein said receive circuit comprises:
a plurality of sample and hold circuits, each configured for sampling and holding one sample of the received electrical signals over one code length; and
an operational amplifier configured as a summing operational amplifier, configured to commence integration and integrate said samples after all samples from an entire received pulse have been acquired by said sample and hold units.

16. The system of claim 1 , wherein said receive circuit comprises:
an analog memory bank provided for holding each sample of the received electrical signals over one code length; and
an operational amplifier configured as a summing operational amplifier, configured to commence integration and integrate said samples after all samples from an entire received pulse have been

Assignees

• Walker William F
• Fuller Michael I
• Ranganathan Karthik
• Hossack John A
• Blalock Travis N
• Univ Virginia Patent Foundation

Inventors

• Walker William F
• Fuller Michael I
• Ranganathan Karthik
• Hossack John A
• Blalock Travis N

Classifications

• G01N29/0654 Primary

  Imaging · CPC title

• G01S7/52079

  Constructional features (constructional features of transducers B06B; mounting transducers G10K11/00; constructional features of ultrasonic medical diagnostic devices A61B8/44) · CPC title

• A61B8/00

  Diagnosis using ultrasonic, sonic or infrasonic waves · CPC title

• G01S7/52026

  Extracting wanted echo signals (Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979) · CPC title

• A61B8/4483

  characterised by features of the ultrasound transducer · CPC title