Apparatus and method for estimating a frequency offset, apparatus and method for estimating a channel spacing and system

Patent metadata

Field	Value
Publication number	US-9985801-B2
Application number	US-201715460963-A
Country	US
Kind code	B2
Filing date	Mar 16, 2017
Priority date	Mar 18, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Embodiments of this disclosure provide an apparatus and method for estimating a frequency offset, an apparatus and method for estimating a channel spacing and a system. The apparatus for estimating a frequency offset includes: a synchronization extracting unit configured to perform a training sequence synchronization extraction on a receiving sequence containing a periodic training sequence to obtain the training sequence; a delay correlation processing unit configured to parallelly perform autocorrelation operations of different delay amounts on the training sequence to obtain multiple parallel correlation sequences; a superimposition processing unit configured to perform a superimposition operation on the multiple parallel correlation sequences to obtain a single sequence; and a frequency offset estimating unit configured to determine a frequency offset according to a phase of a synchronization position of the single sequence in the training sequence. With the embodiments of this disclosure, anti-noise characteristic of the frequency offset estimation may be improved.

First claim

What is claimed is:

1. An apparatus for estimating a frequency offset, comprising:
a memory that stores a plurality of instructions; and
a processor coupled to the memory and configured to execute the instructions to:
perform a training sequence synchronization extraction on a receiving sequence containing a periodic training sequence to obtain the training sequence;
parallelly perform autocorrelation operations of different delay amounts on the training sequence to obtain multiple parallel correlation sequences;
perform a superimposition operation on the multiple parallel correlation sequences to obtain a single sequence; and
determine a frequency offset according to a phase of a synchronization position of the single sequence in the training sequence,
wherein the processor is configured to execute the instructions to perform complex conjugate multiplication on two neighboring correlation sequences in the multiple parallel correlation sequences, and then add up all values to obtain the single sequence.

2. The apparatus according to claim 1 , wherein the different delay amounts are integral multiples of a period of the training sequence, respectively.

3. The apparatus according to claim 1 , wherein an expression of the single sequence is:

C
n

=

∑

i
=
1

k
-
1

⁢

⁢

C
n

i
+
1

·

(

C
n
i

)

*

=

exp
⁡

(

j
⁢

⁢
2
⁢
πΔ
⁢

⁢

fm
·
T

)

⁢

∑

i
=
1

k
-
1

⁢

<

⁢

(

n
+

(

i
+
1

)

·
T

)

·

⁢

(

(

n
+

i
·
m

)

·
T

)

>

;

where, C n i+1 and C n i are the two neighboring correlation sequences in the multiple parallel correlation sequences, k is the number of periods of the periodic training sequence, T is a symbol period, m is a period of sub-sequences in the periodic training sequence, Δf is a frequency offset, TS is an extracted training sequence, and ( )* denotes a complex conjugate operation.

4. The apparatus according to claim 3 , wherein the processor is configured to execute the instructions to divides the phase at the synchronization position of the single sequence in the training sequence by a sub-sequence time period to obtain the frequency offset:

Δ
⁢

⁢
f

=

1

2
⁢

π
·
m
·
T

⁢

⁢
angle
⁢

⁢

(

C
sync

)

;

where, angle(C sync ) is the phase at the synchronization position sync of the single sequence C n in the training sequence, 2π is a constant, and mT is the sub-sequence time period.

5. The apparatus according to claim 1 , wherein the apparatus further comprises:
a preprocessor configured to preprocess the receiving sequence containing the periodic training sequence

Assignees

• Fujitsu Ltd

Inventors

• Zhao Ying
• Dou Liang
• Tao Zhenning

Classifications

• H04L2025/0377

  during the reception of training signals · CPC title

• H04L7/0033

  Correction by delay · CPC title

• H04L25/08

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title

• H04L25/022 Primary

  of frequency response · CPC title

• H04L25/0224 Primary

  using sounding signals · CPC title