Multi-layer time-interleaved analog-to-digital convertor (ADC)

Patent metadata

Field	Value
Publication number	US-9985777-B2
Application number	US-201715419063-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Jun 3, 2011
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

First claim

What is claimed is:

1. A system, comprising:
a first track-and-hold device operable to receive an analog input signal and generate a first sampled analog signal according to a first sample rate;
a second track-and-hold device operable to receive the first sampled analog signal and generate a second sampled analog signal according to a second sample rate that is different than the first sample rate;
a third track-and-hold device operable to receive the second sampled analog signal and generate a third sampled analog signal according to a third sample rate that is different than the first sample rate and the second sample rate; and
an analog-to-digital converter operable to receive the third sampled analog signal and generate a digital signal from the third sampled analog signal.

2. The system according to claim 1 , comprising a controller operable to set the first sample rate, the second sample rate, and the third sample rate.

3. The system according to claim 2 , wherein:
the second track-and-hold device comprises a plurality of second-level track-and-hold circuits; and
the controller is operable to determine the second sample rate based on the first sample rate and a number of the plurality of second-level track-and-hold circuits.

4. The system according to claim 2 , wherein:
the third track-and-hold device comprises a plurality of third-level track-and-hold circuits; and
the controller is operable to determine the second sample rate based on the second sample rate and a number of the plurality of third-level track-and-hold circuits.

5. The system according to claim 4 , wherein the analog-to-digital converter comprises a plurality of analog-to-digital converter circuits, a number of the plurality of analog-to-digital converter circuits being equal to the number of the plurality of third-level track-and-hold circuits.

6. The system according to claim 2 , wherein the controller is operable to set the second sample rate and the third sample rate by configuring clock signals applied to the second track-and-hold device and the third track-and-hold device based on a clock signal applied in the first track-and-hold device.

7. The system according to claim 1 , comprising an amplifier that amplifies the analog input signal before the first track-and-hold device.

8. The system according to claim 1 , comprising a first buffer that buffers the first sampled analog signal between the first track-and-hold device and the second track-and-hold device.

9. The system according to claim 1 , comprising a second buffer that buffers the second sampled analog signal between the second track-and-hold device and the third track-and-hold device.

10. The system according to claim 9 , wherein:
the second track-and-hold device comprises a plurality of second-level track-and-hold circuits; and
the second buffer comprises a plurality of second-level buffer circuits, a number of the plurality of second-level buffer circuits being equal to the number of the plurality of second-level track-and-hold circuits.

Assignees

• Maxlinear Inc

Inventors

• Zhu Jianyu
• Peng Sheng-Yu
• Chandler Rodney
• Tiwari Pawan
• Bhatia Rahul
• Fogleman Eric

Classifications

• H04L7/0334 Primary

  Processing of samples having at least three levels, e.g. soft decisions · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/1215 Primary

  using time-division multiplexing · CPC title