Self-adapting phase-locked loop filter for use in a read channel of a heat assisted magnetic recording drive

Patent metadata

Field	Value
Publication number	US-9985775-B2
Application number	US-201615370960-A
Country	US
Kind code	B2
Filing date	Dec 6, 2016
Priority date	Jul 24, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A phase-locked loop (PLL) filter of a read channel includes a filter portion having an input coupled to delay circuitry having an output. The input of the filter portion is configured to receive a phase error signal. A look-up table is coupled to the filter portion. The look-up table comprises phase coefficients and frequency coefficients associated with a plurality of phase error magnitudes. The look-up table is configured to provide one or both of a selected phase coefficient and a selected frequency coefficient based on a magnitude of the phase error signal. The PLL filter is configured to adjust a bandwidth of the filter portion using one or both of the selected phase coefficient and the selected frequency coefficient. A phase signal indicative of estimated phase disturbance is produced at the output of the delay circuitry.

First claim

What is claimed is:

1. An apparatus, comprising:
a loop detector of a read channel of a heat-assisted magnetic recording (HAMR) drive;
a phase detector configured to receive an error signal produced by the loop detector, the phase detector configured to detect a change in a phase error in the error signal and to produce a phase error signal;
a phase-locked loop (PLL) filter configured to receive the phase error signal and produce a phase signal; and
a threshold detector coupled to the phase detector and the PLL filter, the threshold detector configured to compare the change in the phase error signal to a threshold;
wherein the PLL filter is configured to increase its bandwidth in response to the change in phase error signal exceeding the threshold due to a frequency mode hop of a laser diode of the HAMR drive.

2. The apparatus of claim 1 , wherein the PLL filter is configured to adjust a phase coefficient to increase its bandwidth in response to the change in the phase error signal exceeding the threshold.

3. The apparatus of claim 1 , wherein the PLL filter is configured to adjust a frequency coefficient to increase its bandwidth in response to the change in the phase error signal exceeding the threshold.

4. The apparatus of claim 1 , wherein the PLL filter is configured to adjust a phase coefficient and a frequency coefficient to increase its bandwidth in response to the change in the phase error signal exceeding the threshold.

5. The apparatus of claim 1 , wherein:
the PLL filter is configured to adjust one or both of a phase coefficient and a frequency coefficient to increase its bandwidth in response to the change in the phase error signal exceeding the threshold; and
one or both of the phase coefficient and the frequency coefficient are adjusted based on a magnitude and a sign of the phase error signal change.

6. The apparatus of claim 1 , wherein:
the PLL filter is configured to adjust one or both of a phase coefficient and a frequency coefficient to increase its bandwidth in response to the mode hop.

7. The apparatus of claim 1 , wherein the PLL filter transitions from a tracking mode to an acquisition mode in response to the change in the phase error signal exceeding the threshold.

8. The apparatus of claim 1 , comprising:
a clock generator coupled to the PLL filter, the clock generator configured to adjust an analog-to-digital converter clock signal in response to the phase signal.

9. The apparatus of claim 1 , comprising:
an analog-to-digital converter (A/D converter) configured to receive an analog waveform and to produce digitized samples of the analog waveform; and
the loop detector coupled to the A/D converter and configured to receive the digitized samples and to produce the error signal, the loop detector configured to communicate the error signal to the phase detector.

10. The apparatus of claim 1 , comprising:
an analog-to-digital converter (A/D converter) configured to receive an analog waveform and to produce digitized samples of the analog waveform;
the loop detector coupled to the A/D converter and configured to receive the digitized samples and to produce the error signal, the loop detector configured to communicate the error signal to the phase detector; and
a clock generator coupled to the PLL filter and configured to adjust a clock signal in response to the phase signal, the clock generator communicating the adjusted clock signal to the A/D converter.

11. A method, comprising:
producing an error signal by a loop detector of a read channel of a heat-assisted magnetic recording (HAMR) drive;
receiving the error signal by a phase-locked loop (PLL) filter;
detecting a change in a phase error of the error signal and producing a phase error signal;
comparing the change in the phase error signal to a threshold; and
increasing a bandwidth of the PLL filter in response to the change in the phase error signal exceeding the threshold due to a frequency mode hop of a laser diode of the HAMR drive.

12. The method of claim 11 , wherein the bandwidth of the PLL filter is increased in response to adjustment of a phase coefficient.

13. The method of claim 11 , wherein the bandwidth of the PLL filter is increased in response to adjustment of a frequency coefficient.

14. The method of claim 11 , wherein the bandwidth of the PLL filter is increased in response to adjustment of a phase coefficient and a frequency coefficient.

15. The method of claim 11 , wherein:
increasing the PLL filter bandwidth comprises adjusting one or both of a phase coefficient and a frequency coefficient in response to the change in the phase error signal exceeding the threshold; and
one or both of the phase coefficient and the frequency coefficient are adjusted based on a magnitude and a sign of the phase error signal change.

16. The method of claim 11 , wherein:
increasing the PLL filter bandwidth comprises adjusting one or both of a phase coefficient and a frequency coefficient to increase its bandwidth in response to the mode hop.

17. The method of claim 11 , wherein the PLL filter transitions from a tracking mode to an acquisition mode in response to the change in the phase error signal exceeding the threshold.

18. The method of claim 11 , comprising:
receiving an analog waveform and producing digitized samples of the analog waveform using an analog-to-digital converter (A/D converter); and
adjusting a clock signal by a clock generator coupled to the PLL filter in response to the phase signal; and
communicating the adjusted clock signal to the A/D converter.

Assignees

• Seagate Technology Llc

Inventors

• Patapoutian Ara
• Derras Belkacem
• Radich William Michael
• Link Michael J
• Buch Bruce D

Classifications

• H04L1/0016

  involving special memory structures, e.g. look-up tables · CPC title

• H04L27/148

  using filters, including PLL-type filters · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title