Methods and systems for synchronization between multiple clock domains

Patent metadata

Field	Value
Publication number	US-9985774-B2
Application number	US-201715481407-A
Country	US
Kind code	B2
Filing date	Apr 6, 2017
Priority date	Oct 6, 2014
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

First claim

The invention claimed is:

1. A device for gradual clock synchronization, comprising:
a cascade of multiple First In First Out (FIFO) blocks coupleable between a first clock domain comprising circuits clocked by a first clock and a second clock domain comprising circuits clocked by a second clock;
wherein two adjacent FIFO blocks include data storage FIFOs that are connected in parallel to each other via:
a fixed delay circuit;
a data computation block configured to perform computations on data; and
a synchronizer coupled in parallel to the data computation block and configured to synchronize signals output from the second clock domain to the first clock domain; and
wherein the data computations through the data computation block occur in parallel to clock synchronization through the synchronizer.

2. The device of claim 1 , wherein the fixed delay circuit delays a signal passing through by a time that is equal to a worst case delay through the data computation block.

3. The device of claim 1 , wherein the FIFO stage locks data values computed by the data computational block only after ascertaining stability of the data values.

4. The device of claim 3 , wherein the synchronizer uses a clock transition to make a determination of stability of the data values.

5. The device of claim 1 , wherein the synchronizer changes values of at least some data processed through the synchronizer.

6. The device of claim 1 , wherein the first clock domain is an asynchronous clock domain and wherein the second clock domain is a synchronous clock domain.

7. The device of claim 6 , wherein the data storage FIFOs are driven by a two-phase clock.

8. The device of claim 6 , wherein the data storage FIFOs are driven by a four-phase clock.

9. The device of claim 1 , wherein the first clock domain is a synchronous clock domain and wherein the second clock domain is an asynchronous clock domain.

10. The device of claim 9 , wherein the data storage FIFOs are driven by one of a two-phase clock and a four-phase clock.

11. A method performed by a first FIFO block of a device, comprising:
receiving a request signal passing through a synchronizer block from a second FIFO block connected to a second clock domain comprising circuits clocked by a second clock, wherein the first FIFO block is connected to a first clock domain comprising circuits clocked by a first clock, the second FIFO block receives data from the second clock domain, the first FIFO block sends data to the first clock domain, and the synchronizer block synchronizes signals output from the second clock domain to the first clock domain;
receiving a data input signal from the second FIFO block passing through a data computation block placed between the first FIFO block and the second FIFO block, and
performing, using a data computation block, computations on data in parallel with the synchronizer synchronizing signals other than the data.

12. The method of claim 11 , further comprising:
acknowledging receipt of the request signal received by the first FIFO block; and
issuing a second request to a next stage of the device.

13. The method of claim 11 , further comprising:
processing the data input signal to change a value of the data input signal.

14. The method of claim 13 , further comprising:
making a determination, at a clock edge, whether the value of the data input signal after change is stable.

Assignees

• Univ Cornell

Inventors

• Manohar Rajit
• Jackson Sandra J

Classifications

• H04L47/6245

  Modifications to standard FIFO or LIFO · CPC title

• H04L7/0037 Primary

  Delay of clock signal · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title