On-chip randomness generation

Patent metadata

Field	Value
Publication number	US-9985615-B2
Application number	US-201715421465-A
Country	US
Kind code	B2
Filing date	Feb 1, 2017
Priority date	Jan 11, 2013
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

First claim

What is claimed is:

1. A noise generating apparatus comprising:
a zener diode located on a primary surface of a silicon substrate, wherein the zener diode comprises a P-doped silicon layer on the primary surface of the silicon substrate, and an N-doped polysilicon feature extending up from the P-doped silicon layer, the N-doped polysilicon feature having an upper portion that is wider than a lower portion, the zener diode further comprising spacers covering opposite sides of the lower portion of the N-doped polysilicon feature;
a voltage source located on the silicon substrate to provide a supply voltage;
a current probe for receiving the supply voltage from the voltage source and providing a voltage to the zener diode, the current probe mirroring the current through the zener diode; and
a current monitor located on the silicon substrate to monitor current through the zener diode and adjust the supply voltage provided by the voltage source to maintain the zener diode in an avalanche zone close to a breakdown condition, the current monitor operable to receive the mirrored current from the current probe, the current monitor comprising a trans-impedance amplifier to monitor the current from the current probe and provide an output voltage, wherein the current monitor provides a decrement signal to the voltage source when the output voltage is below a first zener threshold voltage, and an increment signal to the voltage source when the output voltage is above a second zener threshold voltage.

2. The apparatus of claim 1 , wherein the P-doped silicon layer is heavily doped with a p-type dopant with a concentration greater than 10 18 cm −3 , and the N-doped polysilicon feature is heavily doped with an n-type dopant with a concentration greater than 10 18 cm −3 such that the zener diode breaks down at 1.5 volts with a safe operating range from 1.4 volts to 1.6 volts.

3. The apparatus of claim 1 , wherein the voltage source comprises a counter and a digital to analog converter, wherein the digital to analog converter provides an adjustable voltage to the non-inverting input of an operational amplifier, the operational amplifier providing the supply voltage.

4. The apparatus of claim 1 , wherein the zener diode comprises a multi-finger structure comprising multiple N-doped polysilicon features extending up from the P-doped silicon layer, wherein the multiple N-doped polysilicon features are arranged adjacent one another in a straight line, the multi-finger structure further comprising silicide contacts located on the surface of P-doped silicon layer between adjacent N-doped polysilicon features and silicide contacts located on an upper surface of the N-doped polysilicon features.

5. The apparatus of claim 1 , wherein the zener diode breaks down at 1.5 volts with a safe operating range from 1.4 volts to 1.6 volts.

6. The apparatus of claim 1 , wherein a noise signal, received from a different noise generating apparatus, is provided to an amplifier in the voltage source via a resistor.

7. A noise generating apparatus comprising:
two noise generating units each comprising:
an adjustable voltage source on a silicon substrate to provide a supply voltage;
a current probe comprising a first MOSFET and a second MOSFET for receiving the supply voltage from the adjustable voltage source, the first MOSFET and the second MOSFET of the current probe form a current mirror;
a zener diode located on a primary surface of the silicon substrate, the zener diode comprises a P-doped silicon layer on the primary surface of the silicon substrate, and an N-doped polysilicon feature extending up from the P-doped silicon layer, the N-doped polysilicon feature having an upper portion that is wider than a lower portion, the zener diode further comprising spacers covering opposite sides of the lower portion of the N-doped polysilicon feature such that a width of the upper portion of the N-doped polysilicon feature is equal to a combined width of the lower portion of the N-doped polysilicon feature and a width of both spacers, and the zener diode receives the supply voltage from the first MOSFET of the current probe; and
a current monitor located on the silicon substrate to monitor current through the zener diode and adjust the supply voltage provided by the adjustable voltage source to maintain the zener diode in an avalanche zone close to a breakdown condition, the current monitor comprising a trans-impedance amplifier to monitor the current received from the second MOSFET of the current probe, and provide an output voltage to a first operational amplifier and a second operational amplifier such that the first operational amplifier compares the output voltage of the trans-impedance amplifier to a first threshold voltage and the second operational amplifier compares the output voltage of the trans-impedance amplifier to a second threshold voltage,

wherein the noise signal from one noise generating unit is provided to the non-inverting input of an operational amplifier and the noise signal from the other noise generating unit is provided to the inverting input of the operational amplifier such that a resulting noise signal output from the operational amplifier is increased by a factor of √{square root over (2)} from the noise signal of either of the two noise generating units alone.

8. The apparatus of claim 7 , wherein the P-doped silicon layer is heavily doped with a p-type dopant with a concentration greater than 10 18 cm −3 , and the N-doped polysilicon feature is heavily doped with an n-type dopant with a concentration greater than 10 18 cm −3 , and wherein the lower portion of the N-doped polysilicon feature, the upper portion of the N-doped polysilicon feature, and the spacers have a common thickness.

9. The apparatus of claim 7 , wherein the adjustable voltage source comprises a counter and a digital to analog converter, wherein the digital to analog converter provides an adjustable voltage to the non-inverting input of an operational amplifier via a resistor, a fixed voltage is also provide to the non-inverting input of the operational amplifier, and the operational amplifier provides the supply voltage to the first MOSFET and the second MOSFET of the current probe.

10. The apparatus of claim 7 , wherein the zener diode breaks down at 1.5 volts with a safe operating range from 1.4 volts to 1.6 volts.

11. The apparatus of claim 7 , wherein the adjustable voltage source comprises an operational amplifier, wherein the non-inverting input of the operational amplifier is coupled to the output of a digital to analog converter which receives the output from a counter which receives the output of both the first operational amplifier and the second operational amplifier of the current monitor via a first AND gate and a second AND gate.

12. The apparatus of claim 7 , wherein the trans-impedance amplifier comprises a resistor and an operational amplifier, outputs of which are coupled to the inverting input of the first operational amplifier and the non-inverting input of the second operational amplifier, both of the current monitor.

13. The apparatus of claim 7 , wherein the voltage at the input to the zener diode is provided to a first terminal of a capacitor, and a second terminal of the capacitor outputs a noise signal of the noise generating apparatus.

14. A noise generating apparatus comprising:
an adjustable voltage source on a silicon substrate to provide a supply voltage, the adjustable voltage source comprises a counter, a digital to analog converter, a first resistor, a second resistor, and a closed loop operational amplifier, the digital to analog converter receives an o

Assignees

• IBM

Inventors

• Feng Kai D
• Wang Ping-Chuan
• Yang Zhijian
• Yashchin Emmanuel

Classifications

• H03K3/313

  by the use, as active elements, of semiconductor devices with two electrodes, one or two potential barriers, and exhibiting a negative resistance characteristic · CPC title

• H03K3/84 Primary

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• H03K5/01

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title