Power conversion apparatus configured to include plurality of power converter circuits of inverter circuits

Patent metadata

Field	Value
Publication number	US-9985552-B2
Application number	US-201615516948-A
Country	US
Kind code	B2
Filing date	Jan 4, 2016
Priority date	Jan 5, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

In a power converter apparatus, a first power converter circuit is configured of first power semiconductor devices, and a second power converter circuit is connected in parallel to the first power converter circuit, and is configured of second power semiconductor devices. A control circuit generates a control signal for controlling each power semiconductor device of the first and second power converter circuits. A timing control signal generator circuit compares a first amount of current flowing through the first power semiconductor devices with a second amount of current flowing through the second power semiconductor devices, and generate a timing control signal for controlling a timing of a rise or a fall of each of the control signals inputted to the first and second power converter circuits, based on a comparison result. A timing correction circuit controls the control signals to correct the timing of the rise or the fall thereof.

First claim

The invention claimed is:

1. A power converter apparatus comprising:
a first power converter circuit configured of a plurality of first power semiconductor devices;
a second power converter circuit connected in parallel to the first power converter circuit, and configured of a plurality of second power semiconductor devices;
a control circuit configured to generate a control signal for controlling each of the power semiconductor devices of the first power converter circuit and the second power converter circuit;
a timing control signal generator circuit configured to compares a first amount of current flowing through the first power semiconductor devices with a second amount of current flowing through the second power semiconductor devices, and generate a timing control signal for controlling a timing of a rise or a fall of each of the control signals inputted to the first and second power converter circuits, based on a comparison result; and
a timing correction circuit configured to control the control signals inputted to the first and second power converter circuits to correct the timing of the rise or the fall of each of the control signals, or to correct the timing of the rise and the fall of each of the control signals, based on the timing control signal;
a first comparator configured to compare the first amount of current with the second amount of current, and then, when the first amount of current is larger than the second amount of current, generate a first comparison result signal having a high level;
a second comparator configured to compare the first amount of current with the second amount of current, and then, when the first amount of current is equal to or smaller than the second amount of current, generate a second comparison result signal having a high level;
a rising edge detector circuit configured to detect a rising edge of the control signal, and generate a rising edge detection signal; and
a falling edge detector circuit configured to detect a falling edge of the control signal, and generate a falling edge detection signal,
wherein the timing control signal generator circuit includes first and second timing control signal generator circuits,
wherein the first timing control signal generator circuit calculates a value of a first logical product of the first comparison result signal and the rising edge detection signal, calculates a value of a second logical product of the first comparison result signal and the falling edge detection signal, and generates a first timing control signal, based on one of the value of the first logical product and the value of the second logical product, and
wherein the second timing control signal generator circuit calculates a value of a third logical product of the second comparison result signal and the rising edge detection signal, calculates a value of a fourth logical product of the second comparison result signal and the falling edge detection signal, and generates a second timing control signal, based on one of the value of the third logical product and the value of the fourth logical product.

2. The power converter apparatus as claimed in claim 1 , further comprising:
a first counter circuit configured to count a number of generations of the first timing control signal,
wherein the timing correction circuit includes first and second timing correction circuits, and
wherein the first counter circuit outputs the first timing control signal to the first timing correction circuit when the number of generations of the first timing control signal reaches a predetermined first counter value,
wherein the power converter apparatus further comprises:
a second counter circuit configured to count the number of generations of the second timing control signal, and
wherein the second counter circuit outputs the second timing control signal to the second timing correction circuit when the number of generations of the second timing control signal reaches a predetermined second counter value.

3. The power converter apparatus as claimed in claim 2 ,
wherein the first timing correction circuit controls the timing of the rise or the fall of the control signal inputted to the first power converter circuit, based on the first counter value, and
wherein the second timing correction circuit controls the timing of the rise or the fall of the control signal inputted to the second power converter circuit, based on the second counter value.

4. The power converter apparatus as claimed in claim 1 ,
wherein the first power converter circuit includes first to third half bridge circuits, each of the first to third half bridge circuits having a power semiconductor device of a first arm and a power semiconductor device of a second arm connected in series to each other, the first to third half bridge circuits being connected in parallel to each other, and
wherein the second power converter circuit includes fourth to sixth half bridge circuits, each of fourth to sixth half bridge circuits having a power semiconductor device of a third arm and a power semiconductor device of a fourth arm connected in series to each other, the fourth to sixth half bridge circuits being connected in parallel to each other.

5. The power converter apparatus as claimed in claim 4 , further comprising:
first to third resistors connected in series to the first to third half bridge circuits, respectively; and
fourth to sixth resistors connected in series to the fourth to sixth half bridge circuits, respectively,
wherein the first comparator compares the first amount of current with the second amount of current by comparing a voltage difference across one of the first to third resistors with a voltage difference across one of the fourth to sixth resistors, and
wherein the second comparator compares the first amount of current with the second amount of current by comparing a voltage difference across one of the first to third resistors with a voltage difference across one of the fourth to sixth resistors.

6. The power converter apparatus as claimed in claim 4 ,
wherein the first power converter circuit is sealed in a first power module,
wherein the first power module has first to seventh terminals,
wherein the first terminal is a power supply terminal, and is connected to one terminal of each of the first to third half bridge circuits,
wherein the second to fourth terminals are connected to the other terminals of the first to third half bridge circuits, respectively,
wherein each of the fifth to seventh terminals is connected to a connection portion between the power semiconductor device of the first arm and the power semiconductor device of the second arm,
wherein the second power converter circuit is sealed in a second power module,
wherein the second power module has eighth to fourteenth terminals,
wherein the eighth terminal is a power supply terminal, and is connected to one terminal of each of the fourth to sixth half bridge circuits,
wherein the ninth to eleventh terminals are connected to the other terminals of the fourth to sixth half bridge circuits, respectively, and
wherein each of the twelfth to fourteenth terminals is connected to a connection portion between the power semiconductor device of the third arm and the power semiconductor device of the fourth arm.

7. The power converter apparatus as claimed in claim 6 , further comprising first and second heat sinks,
wherein the first power module is mounted on the first heat sink, and the second power module is mounted on the second heat sink.

8. The power converter apparatus as claimed in claim 1 ,
wherein the first power semiconductor device and the second power semiconductor device are metal oxide semiconductor field-effect transistors, each of metal oxid

Assignees

• Mitsubishi Electric Corp

Inventors

• Ikarashi Hiroshi
• Okawa Futoshi
• Nakamura Hiroyuki

Classifications

• H02M7/537

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M7/003 Primary

  Constructional details, e.g. physical layout, assembly, wiring or busbar connections · CPC title

• H05K7/209

  Heat transfer by conduction from internal heat source to heat radiating structure (H05K7/20909 takes precedence) · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title

• H02M7/493

  the static converters being arranged for operation in parallel · CPC title