Sampling implementation method and device based on conventional sampling goose trip mode

Patent metadata

Field	Value
Publication number	US-9985428-B2
Application number	US-201615261173-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Sep 9, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Sampling implementation method and device based on conventional sampling GOOSE trip mode. CPU of master NPI plug-in, after receiving a second pulse, transmits sampling pulse generation time and a transmission enable bit to FPGA of the master NPI plug-in at a fixed interval; after detecting the transmission enable bit, the FPGA of the master NPI plug-in judges whether time of its internal timer is greater than/equal to the sampling pulse generation time, if yes, generates a sampling pulse to FPGA of collection plug-in; after receiving sampling pulse, the collection plug-in carries out A/D sampling, and transmits sampled data to the master NPI plug-in; when detecting that all A/D samplings are completed, the master NPI plug-in transmits data packets to protection CPU plug-in. The device includes an MMI plug-in, a protection CPU plug-in, a master NPI plug-in and a collection plug-in. Protection maloperation is thereby reduced.

First claim

What is claimed is:

1. A sampling implementation method based on a conventional sampling Generic Object Oriented Substation Events (GOOSE) trip mode, comprising:
1) transmitting, by a Central Processing Unit (CPU) of a master New Process layer Interface (NPI) plug-in after receiving a one-pulse-per-second (1PPS) pulse, sampling pulse generation time and a transmission enable bit to a Field Programmable Gate Array (FPGA) of the master NPI plug-in at a fixed interval;
2) judging, by the FPGA of the master NPI plug-in after detecting the transmission enable bit, whether time of an internal timer of the FPGA of the master NPI plug-in is greater than or equal to the sampling pulse generation time, if more than or equal to, generating a sampling pulse to an FPGA of a collection plug-in, and at the same time resetting the transmission enable bit;
3) carrying out Analog-to-Digital (A/D) sampling by the collection plug-in after receiving the sampling pulse of master NPI plug-in, and packing sampled data and transmitting data packets to the master NPI plug-in;
4) transmitting, by the FPGA of the master NPI plug-in when detecting that all the A/D samplings are completed, a sampling completion identifier to the CPU unit of the master NPI plug-in, and transmitting the data packets to a protection CPU plug-in for logical judgment.

2. The sampling implementation method based on the conventional sampling GOOSE trip mode of claim 1 , wherein when there are many analog quantity collection circuits, a slave NPI plug-in is provided, the CPU of the master NPI plug-in and that of the slave NPI plug-in receive the 1PPS pulse simultaneously, carry out the A/D sampling following the Steps 1) to 3); FPGA of the master/slave NPI plug-in, when detecting that all the A/D samplings are completed, transmits the sampling completion identifier to the CPU of the master/slave NPI plug-in, caches the data packets, which, after the data sampling of the master NPI plug-in is synchronized with that of the slave NPI plug-in, are transmitted to the protection CPU plug-in together for logical judgment.

3. The sampling implementation method based on the conventional sampling GOOSE trip mode of claim 1 , wherein when carrying out the A/D sampling, double A/D sampling is used.

4. The sampling implementation method based on the conventional sampling GOOSE trip mode of claim 1 , wherein SV digital sampling is compatible by assembling plug-ins.

5. The sampling implementation method based on the conventional sampling GOOSE trip mode of claim 1 , wherein the 1PPS-pulse received by the CPU of the master NPI plug-in is generated by a clock crystal oscillation source of the protection CPU plug-in per se, or is provided by an external electric B code clock source.

6. The sampling implementation method based on the conventional sampling GOOSE trip mode of claim 1 , wherein the fixed internal in the Step 1) is 0.833 seconds.

7. A sampling device based on a conventional sampling GOOSE trip mode for implementing the method of claim 1 , comprising a Man Machine Interface (MMI) plug-in, a protection CPU plug-in and a master NPI plug-in, wherein the device further comprises a collection plug-in.

8. The sampling device based on the conventional sampling GOOSE trip mode according to claim 7 , wherein the device further comprises a pulse extension plug-in, which is an optical-electric conversion module.

9. The sampling device based on the conventional sampling GOOSE trip mode according to claim 7 , wherein for each collection channel, the collection plug-in is provided with two A/D samplers.

Assignees

• Xj Group Corp
• Xj Electric Co Ltd
• Xuchang Xj Software Technology
• State Grid Corp China
• Xj Electric Co Ltd
• Xuchang Xj Software Technology

Inventors

• Chen Jirui
• Deng Maojun
• Ni Chuankun
• Lv Lijuan
• Ma Heke
• Yao Dongxiao
• Li Baowei
• Li Xu
• Huang Jidong
• Xiao Feng
• Hu Shasha
• Zhang Jingli
• Xi Yingying

Classifications

• H02H7/261 Primary

  involving signal transmission between at least two stations (transmission of signals in general H02H1/0061) · CPC title