Passivated contact formation using ion implantation

Patent metadata

Field	Value
Publication number	US-9985159-B2
Application number	US-201615349630-A
Country	US
Kind code	B2
Filing date	Nov 11, 2016
Priority date	Nov 13, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Methods for forming passivated contacts include implanting compound-forming ions into a substrate to about a first depth below a surface of the substrate, and implanting dopant ions into the substrate to about a second depth below the surface. The second depth may be shallower than the first depth. The methods also include annealing the substrate.

First claim

What is claimed is:

1. A method comprising, in order:
by ion-implantation, implanting a first element as a first ion into a first region of a substrate at a first depth below a surface of the substrate;
by ion-implantation, implanting a second element as a second ion into a second region of the substrate at a second depth below the surface, the second depth being between the surface and the first depth; and
annealing the substrate, wherein:
the substrate comprises a semiconductor,
the first ion is different from the second ion,
the annealing converts the second region to a second layer comprising the second element and the semiconductor,
the annealing converts the first region to a first layer comprising the first element and the semiconductor,
a first unconverted layer of the substrate remains after the annealing, such that the first layer is between the second layer and the first unconverted layer, and
the annealing forms at least one pinhole area through the first layer such that at least a portion of the second element is capable of diffusing through the at least one pinhole area from the second layer to the first unconverted layer.

2. The method of claim 1 , wherein the first layer has a thickness between greater than zero Å and less than 100 Å.

3. The method of claim 1 , wherein the second layer has a monocrystalline structure.

4. The method of claim 3 , further comprising, before the implanting the first element, depositing an additional layer on the surface by an epitaxial method.

5. The method of claim 1 , further comprising, after the annealing, depositing a metal on the second layer to form a low resistance contact.

6. The method of claim 5 , wherein the metal comprises at least one of aluminum, nickel, or silver.

7. The method of claim 6 , wherein the low resistance contact is interdigitated.

8. The method of claim 1 , further comprising
an additional annealing of the substrate prior to the implanting the second element.

9. The method of claim 1 , wherein:
the first depth is between about 20 nanometers and about 300 nanometers, and
the second depth is between about 10 nanometers and about 300 nanometers.

10. The method of claim 1 , wherein the first element comprises oxygen.

11. The method of claim 10 , wherein the first element further comprises at least one of hafnium or nitrogen.

12. The method of claim 1 , wherein the second element comprises at least one of phosphorus, arsenic, antimony, boron, aluminum, indium, or gallium.

13. The method of claim 1 , wherein the semiconductor comprises monocrystalline silicon.

14. The method of claim 13 , wherein:
after the implanting of the first element and the implanting of the second element, the first layer and the second layer are substantially amorphous,
after the implanting of the first element and the implanting of the second element, a second unconverted substrate layer exists between the first layer and the second layer, and
the annealing converts at least a portion of at least one of the first layer or the second layer to a monocrystalline form.

15. The method of claim 13 , wherein:
after the implanting of the first element and the implanting of the second element, the first layer and the second layer are substantially amorphous,
after the implanting of the first element and the implanting of the second element, a third unconverted substrate layer exists between the second layer and the surface, and
the annealing converts at least a portion of at least one of the first layer or the second layer to a monocrystalline form.

16. The method of claim 1 , wherein the annealing is performed by heating the substrate to a temperature between 800° C. and 1200° C.

17. The method of claim 16 , wherein the substrate is maintained at the temperature for a period of time between 30 minutes and 90 minutes.

18. The method of claim 1 , wherein the first layer comprises silicon dioxide.

19. The method of claim 18 , wherein the first layer further comprises at least one of silicon nitride or hafnium oxide.

20. A method comprising, in order:
by ion-implantation, implanting a first element as a first ion into a first region of a substrate at a first depth below a surface of the substrate;
by ion-implantation, implanting a second element as a second ion into a second region of the substrate at a second depth below the surface, the second region being between the surface and the first region; and
annealing the substrate, wherein:
the substrate comprises a crystalline semiconductor,
the first ion is different from the second ion,
the annealing converts the first region to a first crystalline layer comprising the first element and the semiconductor,
the first crystalline layer has a thickness between greater than zero Å and less than 100 Å,
the annealing converts the second region to a second crystalline layer comprising the second element and the semiconductor,
the first layer is capable of transporting carriers between the second layer and an unconverted layer of the substrate, and
the first layer is between the second layer and the unconverted layer.

Assignees

• Alliance Sustainable Energy

Inventors

• Young David L
• Stradins Pauls
• Nemeth William

Classifications

• H01L31/0687

  Electricity · mapped topic

• H01L31/0682

  Electricity · mapped topic

• H01L31/022425

  Electricity · mapped topic

• H01L31/02363

  Electricity · mapped topic

• H01L31/061 Primary

  Electricity · mapped topic