Lateral MOSFET with buried drain extension layer

Patent metadata

Field	Value
Publication number	US-9985095-B2
Application number	US-201615182658-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Dec 19, 2013
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An integrated circuit containing an extended drain MOS transistor which has a drift layer, an upper RESURF layer over and contacting an upper surface of the drift layer, and a buried drain extension below the drift layer which is electrically connected to the drift layer at the drain end and separated from the drift layer at the channel end. A lower RESURF layer may be formed between the drift layer and the buried drain extension at the channel end. Any of the upper RESURF layer, the drift layer, the lower RESURF layer and the buried drain extension may have a graded doping density from the drain end to the channel end. A process of forming an integrated circuit containing an extended drain MOS transistor which has the drift layer, the upper RESURF layer, and the buried drain extension.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a semiconductor substrate having a first conductivity type; and
an extended drain metal oxide semiconductor (EDMOS) transistor, including:
a drain region having a second conductivity type opposite of the first conductivity type;
a drain layer extending from and under the drain region, the drain layer having the second conductivity type;
a channel region adjacent to the drain layer, the channel region having the first conductivity type;
a source region separated from the drain layer by the channel region, the source region having the second conductivity type;
a doped region positioned within the drain layer and separated from the source region and the drain region, the doped region having the first conductivity type; and
a second doped region under the doped region and the drain layer, and extending below the source region, the second doped region having the first conductivity type,
wherein the doped region is closer to the drain region along a lateral direction than the second doped region.

2. The integrated circuit of claim 1 , wherein the EDMOS transistor includes:
a buried drain layer extending under the drain layer and overlapping the channel region and the source region, the buried drain layer having the second conductivity type.

3. The integrated circuit of claim 2 , wherein the second doped region interposed partially between the drain layer and the buried drain layer.

4. The integrated circuit of claim 1 , wherein the EDMOS transistor includes:
a backgate region surrounding the source region, the backgate region having the first conductivity type; and
an isolation structure extending from a top surface of the semiconductor substrate and having a connection with the drain layer under the backgate region, the isolation structure laterally surrounding the backgate region with the drain layer, the isolation structure having the second conductivity type.

5. The integrated circuit of claim 4 , wherein the EDMOS transistor includes:
a body region positioned within the backgate region and adjacent to the source region, the body region laterally surrounded by the isolation structure and the drain layer.

6. The integrated circuit of claim 4 , wherein the connection includes a drain buried layer connected between and under the isolation structure and the drain layer, the drain buried layer having the second conductivity type, and extending under the backgate region.

7. The integrated circuit of claim 1 , wherein the first conductivity type includes a p-type material, and the second conductivity type includes an n-type material.

8. The integrated circuit of claim 1 , wherein the first conductivity type includes an n-type material, and the second conductivity type includes an p-type material.

9. The integrated circuit of claim 1 , wherein the doped region having a first doping density near the drain region and a second doping density near the source region and higher than the first doping density.

10. An extended drain metal oxide semiconductor (EDMOS) transistor, comprising:
a semiconductor substrate having a first conductivity type;
a drain region having a second conductivity type opposite of the first conductivity type;
a drain layer extending from and under the drain region, the drain layer having the second conductivity type;
a channel region adjacent to the drain layer, the channel region having the first conductivity type;
a source region separated from the drain layer by the channel region, the source region having the second conductivity type;
a doped region positioned within the drain layer and separated from the source region and the drain region, the doped region having the first conductivity type; and
a second doped region under the doped region and the drain layer, and extending below the source region, the second doped region having the first conductivity type,
wherein the doped region is closer to the drain region along a lateral direction than the second doped region.

11. The EDMOS transistor of claim 10 , further comprising:
a buried drain layer extending under the drain layer and overlapping the channel region and the source region, the buried drain layer having the second conductivity type.

12. The EDMOS transistor of claim 11 , wherein the second doped region interposed partially between the drain layer and the buried drain layer.

13. The EDMOS transistor of claim 10 , further comprising:
a backgate region surrounding the source region, the backgate region having the first conductivity type; and
an isolation structure extending from a top surface of the semiconductor substrate and having a connection with the drain layer under the backgate region, the isolation structure laterally surrounding the backgate region with the drain layer, the isolation structure having the second conductivity type.

14. The EDMOS transistor of claim 13 , further comprising:
a body region positioned within the backgate region and adjacent to the source region, the body region laterally surrounded by the isolation structure and the drain layer.

15. The EDMOS transistor of claim 13 , wherein the connection includes a drain buried layer connected between and under the isolation structure and the drain layer, the drain buried layer having the second conductivity type, and extending under the backgate region.

16. The EDMOS transistor of claim 10 , wherein the first conductivity type includes a p-type material, and the second conductivity type includes an n-type material.

17. The EDMOS transistor of claim 10 , wherein the first conductivity type includes an n-type material, and the second conductivity type includes an p-type material.

18. The EDMOS transistor of claim 10 , wherein the doped region having a first doping density near the drain region and a second doping density near the source region and higher than the first doping density.

Assignees

• Texas Instruments Inc

Inventors

• Denison Marie
• Hower Philip L
• Pendharkar Sameer

Classifications

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P30/22

  using masks · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title