Array substrate

Patent metadata

Field	Value
Publication number	US-9985053-B2
Application number	US-201615054884-A
Country	US
Kind code	B2
Filing date	Feb 26, 2016
Priority date	Aug 13, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An array substrate and a display apparatus including the array substrate. The array substrate includes: a plurality of signal lines aligned in a display area of the array substrate; a plurality of signal pads aligned in a non-display area of the array substrate; a plurality of fan-out lines aligned in the non-display area and respectively connected to the signal lines and the signal pads; a plurality of auxiliary lines respectively overlapping and insulated from the fan-out lines; and a plurality of connection lines connecting in parallel at least two of the auxiliary lines that are adjacent to each other.

First claim

What is claimed is:

1. An array substrate comprising:
a plurality of signal lines aligned in a display area of the array substrate;
a plurality of signal pads aligned in a non-display area of the array substrate;
a plurality of fan-out lines aligned in the non-display area and respectively connected to the signal lines and the signal pads;
a plurality of auxiliary lines respectively overlapping and insulated from the fan-out lines; and
a plurality of connection lines connecting in parallel at least two of the auxiliary lines that are adjacent to each other,
wherein each of the auxiliary lines overlaps and extends along a corresponding one of the fan-out lines.

2. The array substrate of claim 1 , wherein the connection lines are integrally formed with the auxiliary lines.

3. The array substrate of claim 1 , wherein the connection lines are electrically connected to the auxiliary lines through a contact hole formed in an insulating layer disposed between the connection lines and the auxiliary lines.

4. The array substrate of claim 1 , wherein the connection lines comprise:
a first connection line connecting first ends of the auxiliary lines; and
a second line connecting second ends of the auxiliary lines.

5. The array substrate of claim 1 , further comprising at least one insulation pattern arranged on at least one of the first and second ends of each of the auxiliary lines.

6. The array substrate of claim 5 , wherein the at least one insulation pattern comprises a blue color filter material.

7. The array substrate of claim 1 , wherein:
the fan-out lines comprise a first area and a second area; and
the fan-out lines have straight line shapes, spaces between the fan-out lines decrease toward the signal pads from the signal lines in the first area, and the fan-out lines have a zigzag pattern and spaces between the fan-out lines are constant in the second area.

8. The array substrate of claim 7 , wherein, in the second area, a length of the zigzag pattern decreases from a center portion of the zigzag pattern to an outer portion of the zigzag pattern.

9. The array substrate of claim 1 , wherein the signal lines comprise:
a plurality of gate lines extending in a first direction; and
a plurality of data lines extending in a second direction crossing the first direction.

10. The array substrate of claim 9 , wherein:
the fan-out lines are aligned at a same level as the plurality of gate lines; and
the auxiliary lines are aligned at a same level as the data lines.

11. An array substrate comprising:
a plurality of signal lines aligned in a display area of the array substrate;
a plurality of signal pads aligned in a non-display area of the array substrate;
a plurality of fan-out lines aligned in the non-display area and respectively connected to the signal lines and the signal pads;
a plurality of auxiliary lines respectively overlapping the fan-out lines, at least one end of each of the auxiliary lines being electrically connected to a corresponding one of the fan-out lines; and
a plurality of connection lines connecting in parallel at least two of the auxiliary lines that are adjacent to each other,
wherein each of the auxiliary lines overlaps and extends along a corresponding one of the fan-out lines.

12. The array substrate of claim 11 , wherein the connection lines are integrally formed with the auxiliary lines.

13. The array substrate of claim 11 , wherein the connection lines are electrically connected to the auxiliary lines through a contact hole formed in an insulating layer disposed between the connection lines and the plurality of auxiliary lines.

14. The array substrate of claim 11 , wherein the connection lines comprise:
a first connection line connecting first ends of the auxiliary lines; and
a second connection line connecting second ends of the auxiliary lines.

15. The array substrate of claim 11 , further comprising at least one insulation pattern arranged on at least one of the first and second ends of each of the auxiliary lines.

16. The array substrate of claim 15 , wherein the at least one insulation pattern comprises a blue color filter material.

17. The array substrate of claim 11 , wherein:
the fan-out lines comprise a first area and a second area; and
the fan-out lines have straight line shapes, spaces between the fan-out lines decrease toward the signal pads from the signal lines in the first area, and the fan-out lines have a zigzag pattern and spaces between the fan-out lines are constant in the second area.

18. The array substrate of claim 17 , wherein, in the second area, a length of the zigzag pattern decreases from a center portion of the zigzag pattern to an outer portion of the zigzag pattern.

19. The array substrate of claim 11 , wherein the signal lines comprise:
a plurality of gate lines extending in a first direction; and
a plurality of data lines extending in a second direction crossing the first direction.

20. The array substrate of claim 19 , wherein:
the fan-out lines are aligned at a same level as the gate lines, and
the auxiliary lines are aligned at a same level as the data lines.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Kyungho
• Ki Donghyeon
• Park Kiwon
• Shin Donghee

Classifications

• G02F1/1345

  Conductors connecting electrodes to cell terminals · CPC title

• G02F1/136259

  Repairing; Defects · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• H01L27/1248

  Electricity · mapped topic

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title