Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9984959-B2
Application number	US-201615162271-A
Country	US
Kind code	B2
Filing date	May 23, 2016
Priority date	Aug 7, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An object of the present invention is to improve the performance of a semiconductor device that transmits signals using inductive coupling of inductors.
A semiconductor device includes a first semiconductor chip having a first inductor formed on the first top surface side and a second semiconductor chip having a second inductor formed on the second top surface side. The first semiconductor chip and the second semiconductor chip are laminated on each other so that the first top surface and the second top surface face each other. Further, a plurality of first pads of the first semiconductor chip is provided along each of a first chip side and a second chip side among four sides of the first top surface. Further, each of the first pads of the first semiconductor chip is not overlapped with the second semiconductor chip in planar view.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor chip including a first top surface in a quadrangular shape, a first back surface opposite to the first top surface, a plurality of first pads arranged over the first top surface, and a first inductor that is provided on a side of the first top surface and is electrically coupled to the first pads;
a second semiconductor chip including a second top surface in a quadrangular shape, a second back surface opposite to the second top surface, a plurality of second pads arranged over the second top surface, and a second inductor that is provided on a side of the second top surface and is electrically coupled to the second pads, the second inductor being mounted over the first semiconductor chip through an insulating film so as to face the first inductor;
a chip mounting part over which the first semiconductor chip and the second semiconductor chip are mounted;
a plurality of leads mounted around the chip mounting part;
a plurality of first wires through which each of a plurality of first leads of the leads and each of the first pads of the first semiconductor chip are electrically coupled to each other; and
a plurality of second wires through which each of a plurality of second leads of the leads and each of the second pads of the second semiconductor chip are electrically coupled to each other,
wherein the first pads are provided along each of a first chip side and a second chip side intersecting with the first chip side among four sides of the first top surface,
wherein the second semiconductor chip is mounted over the first semiconductor chip in such a manner that each of the first pads of the first semiconductor chip is not overlapped with the second semiconductor chip in a first planar view viewed from the side of the first top surface of the first semiconductor chip and each of the second pads of the second semiconductor chip is not overlapped with the first semiconductor chip in a second planar view viewed from the side of the second top surface of the second semiconductor chip, and
wherein the insulating film is disposed on the first top surface and on the second top surface such that, in the first planar view, an edge of the insulating film overlaps with an edge of the second top surface and another edge of the insulating film is located inside the second top surface.

2. The semiconductor device according to claim 1 , wherein the second semiconductor chip is mounted over the first semiconductor chip in such a manner that each of the second pads is not overlapped with the chip mounting part in the second planar view.

3. The semiconductor device according to claim 1 , wherein a plurality of hanging leads coupled to the chip mounting part is further provided,
wherein the chip mounting part has a first base material side, a second base material side extending in a direction intersecting with the first base material side, a third base material side facing the first base material side, a fourth base material side that faces the second base material side and extends in a direction intersecting with the third base material side, a first corner part formed by the third base material side and the fourth base material side, and a second corner part formed by the first base material side and the second base material side,
wherein the second semiconductor chip is mounted over the first semiconductor chip so as to be overlapped with the first corner part in the first planar view, and
wherein the hanging leads are coupled to parts other than the first corner part and the second corner part of the chip mounting part.

4. The semiconductor device according to claim 1 , wherein an area of a part where a projected part of the second semiconductor chip not overlapped with the first semiconductor chip is overlapped with the chip mounting part is smaller than that of a part where the projected part is not overlapped with the chip mounting part.

5. The semiconductor device according to claim 1 , wherein the first semiconductor chip has the first chip side, the second chip side intersecting with the first chip side, a third chip side facing the first chip side, and a fourth chip side facing the third chip side,
wherein the second semiconductor chip has a fifth chip side arranged so as to be aligned along the first chip side of the first semiconductor chip, a sixth chip side intersecting with the fifth chip side, a seventh chip side facing the fifth chip side, and an eighth chip side facing the sixth chip side,
wherein the chip mounting part has a first base material side arranged so as to be aligned along the first chip side of the first semiconductor chip, a second base material side intersecting with the first base material side, a third base material side facing the first base material side, and a fourth base material side facing the second base material side, and
wherein a first distance from the third chip side of the first semiconductor chip to the third base material side of the chip mounting part is smaller than a second distance from the seventh chip side of the second semiconductor chip to the third base material side of the chip mounting part in the first planar view.

6. The semiconductor device according to claim 5 , wherein a third distance from the fourth chip side of the first semiconductor chip to the fourth base material side of the chip mounting part is smaller than a fourth distance from the eighth chip side of the second semiconductor chip to the fourth base material side of the chip mounting part in the first planar view.

7. The semiconductor device according to claim 6 , wherein third wires are coupled between the first base material side of the chip mounting part and the first chip side of the first semiconductor chip, and
wherein a fifth distance from the first base material side of the chip mounting part to the first chip side of the first semiconductor chip is larger than the first distance.

8. The semiconductor device according to claim 1 , wherein an area of a part where the first semiconductor chip is overlapped with the second semiconductor chip is larger than that of a part where the first semiconductor chip is not overlapped with the second semiconductor chip in the first planar view.

9. The semiconductor device according to claim 1 , wherein a metal film is formed over the second back surface of the second semiconductor chip, and
wherein third leads of the leads are electrically coupled to the metal film of the second back surface through the third wires.

10. The semiconductor device according to claim 9 , wherein the first semiconductor chip and the chip mounting part are electrically coupled to each other through fourth wires coupled to a part of the chip mounting part.

11. The semiconductor device according to claim 1 , wherein the chip mounting part has a first base material side, a second base material side extending in a direction intersecting with the first base material side, a third base material side facing the first base material side, a fourth base material side that faces the second base material side and extends in a direction intersecting with the third base material side, a first corner part formed by the third base material side and the fourth base material side, and a second corner part formed by the first base material side and the second base material side, and
wherein the second semiconductor chip is mounted over the first semiconductor chip so as to be overlapped with the first corner part and so as not to be overlapped with the second corner part in the first planar view.

12. The semiconductor device according to claim 11 , wherein the first semiconductor

Assignees

• Renesas Electronics Corp

Inventors

• Shuto Takao
• Ishihara Kaoru

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title