Semiconductor device having capability of generating chip identification information

Patent metadata

Field	Value
Publication number	US-9984767-B2
Application number	US-201615240863-A
Country	US
Kind code	B2
Filing date	Aug 18, 2016
Priority date	Sep 10, 2012
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

First claim

What is claimed is:

1. A semiconductor device for generating chip identification information, comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns;
a voltage generation circuit configured to supply a power supply voltage to said memory cell array;
a self-diagnostic circuit configured to determine mismatch of write data and read data of each of the plurality of memory cells;
a test address storage unit configured to store a plurality of test addresses; and
an identification information generation circuit;
wherein, when chip identification information is generated,
said voltage generation circuit is configured to lower said power supply voltage;
said self-diagnostic circuit is configured to determine memory cells corresponding to said plurality of test addresses and output fail addresses; and said identification information generation circuit is configured to generate said chip identification information based on said fail addresses.

2. The semiconductor device according to claim 1 , wherein
said test address storage unit is configured to store, as said test address, a defective cell address of said memory cell under a first measurement condition,
said self-diagnostic circuit is configured to output said defective cell address based on a result of operational confirmation, under a third measurement condition, of said memory cell selected by said defective cell address, and
a static noise margin for said memory cell under said first measurement condition is set larger than a static noise margin for said memory cell under said third measurement condition.

3. The semiconductor device according to claim 2 , wherein
said test address storage unit is further configured to store, as said test address, a normal cell address of said memory cell under a second measurement condition,
said self-diagnostic circuit is configured to make operational confirmation, under said third measurement condition, of said memory cell selected by said normal cell address, and
a static noise margin for said memory cell under said third measurement condition is set larger than a static noise margin for said memory cell under said second measurement condition.

4. The semiconductor device according to claim 3 , wherein
said power supply voltage under said first measurement condition is set larger than said power supply voltage under said third measurement condition.

5. The semiconductor device according to claim 4 , wherein said power supply voltage under said third measurement condition is set larger than said power supply voltage under said second measurement condition.

Assignees

• Renesas Electronics Corp

Inventors

• Fujiwara Hidehiro
• Yabuuchi Makoto
• Nii Koji
• Saito Yoshikazu

Classifications

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/12

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C11/417

  for memory cells of the field-effect type · CPC title

• G06K19/0722

  comprising an arrangement for testing the record carrier · CPC title

• G11C29/06

  Acceleration testing · CPC title