Driving Method of Pixel Array, Driving Module of Pixel Array and Display Device
US-2016055808-A1 · Feb 25, 2016 · US
US9984636B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9984636-B2 |
| Application number | US-201514937581-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 10, 2015 |
| Priority date | Dec 30, 2014 |
| Publication date | May 29, 2018 |
| Grant date | May 29, 2018 |
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Provided if a display device including a liquid crystal panel, a common voltage generator configured to generate a common voltage, and a common voltage compensator. The liquid crystal panel includes gate lines, data lines, pixels, and a common electrode. The pixels include first pixels and second pixels. The first pixels and the second pixels are respectively disposed in pixel rows adjacent to each other, respectively constitute different columns, are connected to the same gate line, display the same color, and receive data voltages having different polarities. When a boundary of a pattern included in image data, extending in a first direction, lies between the first pixels and the second pixels, the common voltage compensator is configured to compensate the common voltage.
Opening claim text (preview).
What is claimed is: 1. A display device comprising: a liquid crystal panel which includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction intersecting with the first direction, a plurality of pixels connected to the gate lines and the data lines, and a common electrode, wherein the pixels includes pixels in an h-th (h is a natural number) row and pixels in an (h+1)-th row with a (k+1)-th (k is a natural number) gate line of the gate lines disposed therebetween, wherein the pixels in the h-th row and the pixels in the (h+1)-th row are adjacent to each other in the second direction, and first pixels which display a first color and are connected to the (k+1)-th gate line among the pixels in the h-th row, and second pixels which display the first color and are connected to the (k+1)-th gate line among the pixels in the (h+1)-th row, are spaced from each other in the first direction and receive data voltages having different polarities; a gate driver configured to provide the gate lines with gate signals; a data driver configured to provide the data lines with data voltages; a timing controller which is configured to receive a control signal and image data, provide the gate driver with a gate control signal, and provide the data driver with a data control signal; a common voltage generator configured to generate a common voltage to be applied to the common electrode; and a common voltage compensator which is configured to compensate the common voltage before a (k+1)-th gate signal is applied to the (k+1)-th gate line, in the case where a boundary of a pattern included in the image data, extending in the first direction, lies between the first pixels and the second pixels, wherein when the pattern is displayed in at least a portion of the first pixels and is not displayed in the second pixels, the common voltage compensator is configured to add a first compensating voltage having a polarity opposite to that of data voltages applied to the portion of the first pixels to the common voltage, wherein when the pattern is displayed in at least a portion of the second pixels and is not displayed in the first pixels, the common voltage compensator is configured to add a second compensating voltage having a polarity opposite to that of data voltages applied to the portion of the second pixels to the common voltage. 2. The display device of claim 1 , wherein the common voltage compensator comprises: a pattern analyzer which is configured to analyze the pattern included in the image data to determine whether the boundary of the pattern, extending in the first direction, lies between the first pixels and the second pixels; a compensating section determiner which is configured to determine a compensating section in which the common voltage is to be compensated when the boundary of the pattern, extending in the first direction, lies between the first pixels and the second pixels; and a compensating voltage determiner which is configured to determine the magnitude and polarity of a compensating voltage to be compensated to the common voltage when the boundary of the pattern, extending in the first direction, lies between the first pixels and the second pixels. 3. The display device of claim 2 , wherein the compensating section determiner is configured to set the compensating section to be within a horizontal blank section between a k-th horizontal scanning section in which a k-th gate signal is applied to a k-th gate line and a (k+1)-th horizontal scanning section in which the (k+1)-th gate signal is applied to the (k+1)-th gate line. 4. The display device of claim 3 , wherein the compensating section determiner is configured to set the compensating section to be a section from a first point of time within the horizontal blank section to a point of time at which the (k+1)-th horizontal scanning section starts. 5. The display device of claim 4 , wherein the first point of time is set to be a point of time at which data voltages are applied to the first pixels which display the pattern or a point of time at which data voltages are applied to the second pixels which display the pattern. 6. The display device of claim 2 , wherein the compensating voltage determiner is configured to determine the magnitude of the compensating voltage, based on the number of pixels displaying the pattern among the first pixels and the second pixels and the level of data voltages applied to the pixels displaying the pattern. 7. The display device of claim 6 , wherein when the pattern is displayed in at least a portion of the first pixels and is not displayed at the second pixels, the compensating voltage determiner is configured to set the polarity of the compensating voltage to be opposite to that of data voltages applied to the portion of the first pixels, wherein when the pattern is displayed in at least a portion of the second pixels and is not displayed at the first pixels, the compensating voltage determiner is configured to set the polarity of the compensating voltage to be opposite to that of data voltages applied to the portion of the second pixels. 8. The display device of claim 1 , wherein the first color is any one of red, green, blue, or white. 9. The display device of claim 1 , wherein the pixels in the h-th row comprise first and second pixel groups which are sequentially disposed in the first direction, and the pixels in the (h+1)-th row comprise third and fourth pixel groups which are sequentially disposed in the first direction, each of the first to fourth pixel groups comprising an even number of pixels. 10. The display device of claim 9 , wherein each of the first and fourth pixel groups comprises two pixels among red, green, blue, and white pixels, each of the second and third pixel groups comprises the remaining two pixels among the red, green, blue, and white pixels. 11. The display device of claim 1 , wherein the second pixels are included in pixels in a (2u+1)-th (u is a natural number) column when the first pixels are included in pixels in a (2u−1)-th column, and the second pixels are included in pixels in a (2u+2)-th column when the first pixels are included in pixels in a 2u-th column. 12. The display device of claim 1 , wherein two pixels which are adjacent to each other in the second direction with a 2k-th gate line disposed therebetween, among pixels in a (2u−1)-th (u is a natural number) column, share the 2k-th gate line to be connected to each other, and two pixels which are adjacent to each other in the second direction with a (2k−1)-th gate line disposed therebetween, among pixels in a 2u-th column, share the (2k−1)-th gate line to be connected to each other. 13. The display device of claim 1 , wherein two pixels which are adjacent to each other in the second direction with a (2k−1)-th gate line disposed therebetween, among pixels in a (2u−1)-th (u is a natural number) column, share the (2k−1)-th gate line to be connected to each other, and two pixels which are adjacent to each other in the second direction with a 2k-th gate line disposed therebetween, among pixels in a 2u-th column, share the 2k-th gate line to be connected to each other. 14. The display device of claim 1 , wherein pixels in a u-th (u is a natural number) column, which are disposed between a j-th (j is a natural number) data line and a (j+1)-th data line of the data lines, are alternately connected to the j-th data line and the (j+1)-th data line by every at least one pixel. 15. The display device of claim 14 , wherein the polarities of data voltages a
Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title
Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title
Layout of electrodes and connections · CPC title
Control of polarity reversal in general · CPC title
using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title
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