Computing system control

Patent metadata

Field	Value
Publication number	US-9984015-B2
Application number	US-201415116208-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Feb 28, 2014
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

In one example in accordance with the present disclosure, a computing system is provided. The computing system includes a first bus controller to control X bus lanes, a second bus controller to control Y bus lanes, a 2-to-1 X lane multiplexer, and a Y lane system component, where Y>X>0. X lanes from the first bus controller are coupled to the 2-to-1 X lane multiplexer. X lanes from the second bus controller are coupled to the 2-to-1 X lane multiplexer, and Y-X lanes from the second bus controller are coupled directly to the Y lane system component. In addition, X lanes from the 2-to-1 X lane multiplexer are coupled to the Y lane system component.

First claim

What is claimed is:

1. A computing system comprising:
a first bus controller to control X bus lanes;
a second bus controller to control Y bus lanes;
a 2-to-1 X lane multiplexer, and
a Y lane system component,
wherein Y>X>0,
wherein X lanes from the first bus controller are coupled to the 2-to-1 X lane multiplexer,
wherein X lanes from the second bus controller are coupled to the 2-to-1 X lane multiplexer, and Y-X lanes from the second bus controller are coupled directly to the Y lane system component, and
wherein X lanes from the 2-to-1 X lane multiplexer are coupled to the Y lane system component.

2. The computing system of claim 1 , wherein a first processor comprises the first bus controller, and a second processor comprises the second bus controller.

3. The computing system of claim 2 , wherein the first processor is fixed within the computing system, and the second processor is optional within the computing system.

4. The computing system of claim 1 , wherein the 2-to-1 X lane multiplexer is to select between the X lanes from the first bus controller and the X lanes from the second bus controller based on whether the second bus controller is present within the computing system.

5. The computing system of claim 1 , wherein the first bus controller is to control X Peripheral Component Interconnect Express (PCIe) lanes, and wherein the second bus controller is to control Y PCIe bus lanes.

6. The computing system of claim 1 , wherein the first bus controller is a Peripheral Component Interconnect Express (PCIe) root complex device, and wherein the second bus controller is a PCIe root complex device.

7. The computing system of claim 1 , wherein the Y lane system component comprises a Y lane slot.

8. A computing system comprising:
a first bus controller to control X bus lanes;
a second bus controller to control Y bus lanes;
a 2-to-1 X lane multiplexer;
a Y lane slot; and
system firmware to control operation of at least one of the 2-to-1 X lane multiplexer, the first bus controller and the second bus controller,
wherein Y>X>0,
wherein X lanes from the first bus controller are coupled to the 2-to-1 X lane multiplexer,
wherein X lanes from the second bus controller are coupled to the 2-to-1 X lane multiplexer, and Y-X lanes from the second bus controller are coupled directly to the Y lane slot, and
wherein an X lanes from the 2-to-1 X lane multiplexer are coupled to the Y lane slot.

9. The computing system of claim 8 , wherein the system firmware comprises a basic input/output system (BIOS) or a unified extensible firmware interface (UEFI).

10. The computing system of claim 8 , wherein the system firmware is to control the 2-to-1 X lane multiplexer to select X lanes from the first bus controller, and further control the second bus controller to disable the Y-X lanes from the second bus controller that are coupled directly to the Y lane slot.

11. The computing system of claim 8 , wherein the system firmware is to control the 2-to-1 X lane multiplexer to select the X lanes from the second bus controller.

12. The computing system of claim 8 , wherein the first bus controller is to control X Peripheral Component Interconnect Express (PCIe) lanes, and wherein the second bus controller is to control Y PCIe lanes.

13. A computing system comprising:
a mandatory bus controller;
an optional bus controller;
a 2-to-1 multiplexer; and
a system component,
wherein the 2-to-1 multiplexer is coupled to the mandatory bus controller,
wherein the 2-to-1 multiplexer is also coupled to the optional bus controller,
wherein the system component is coupled to the 2-to-1 multiplexer,
wherein the system component is also coupled directly to the optional bus controller, and
wherein operations of the 2-to-1 multiplexer and the optional bus controller are controllable via system firmware to enable the system component to interact with bus lanes from either the mandatory bus controller or the optional bus controller.

14. The system of claim 13 , wherein the system component comprises an input/output (I/O) slot.

15. The system of claim 13 , wherein the optional bus controller is to control more bus lanes than the mandatory bus controller.

Assignees

• Hewlett Packard Development Co

Inventors

• Pearson Roger A
• Gay Raphael

Classifications

• G06F13/1678 Primary

  using bus width · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title