Conditional selection of data elements

Patent metadata

Field	Value
Publication number	US-9983872-B2
Application number	US-201715666978-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Oct 12, 2010
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

First claim

We claim:

1. A data processing apparatus comprising:
a data store comprising a plurality of storage elements for storing data elements;
an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction comprising a primary source storage element field specifying a primary source storage element, and a secondary source storage element field specifying a secondary source storage element, wherein said at least one conditional select instruction further specifies a condition and an operation to be performed on a data element stored in said secondary source storage element;
a data processor configured to perform data processing operations controlled by said instruction decoder wherein:
said data processor is responsive to said decoded at least one conditional select instruction and said condition having a predetermined outcome to perform said operation on said data element from said secondary source storage element to output a resultant data element;
said data processor is responsive to said decoded at least one conditional select instruction and said condition not having said predetermined outcome to output said data element within said primary source storage element as said resultant data element;
and wherein, when said at least one conditional select instruction is a conditional select invert instruction, said instruction decoder is configured to output an invert control signal; and
said data processor comprises:
an adder configured in response to said invert control signal being set to receive said data value from said secondary source storage element through an inverter and in response to said invert control signal not being set to receive said data value from said secondary source storage element not passed through said inverter;
a multiplexer configured to receive signals from said primary source storage element and from an output of said adder, a select signal for said multiplexer comprising said condition, such that said condition having said predetermined outcome triggers said multiplexer to select said output of said adder.

2. A data processing apparatus according to claim 1 , wherein said instruction further specifies a destination storage element, said data processor being responsive to said at least one conditional select instruction to store said resultant data element in said destination storage element.

3. A data processing apparatus according to claim 2 , wherein said destination storage element comprises one of said primary and secondary source storage elements.

4. A data processing apparatus according to claim 1 , wherein said data processor is responsive to said decoded at least one conditional select instruction and said condition not having said predetermined outcome to perform said operation on said data element within said secondary source storage element and to form said resultant data element from said data element within said primary storage element.

5. A data processing apparatus according to claim 1 , wherein said at least one conditional select instruction comprises an increment conditional select instruction, said operation comprising incrementing said data element from said secondary source storage element.

6. A data processing apparatus according to claim 1 , wherein said at least one conditional select instruction comprises an invert conditional select instruction, said operation comprising logically inverting said data element from said secondary source storage element to generate a logically bitwise inverted storage element value.

7. A data processing apparatus according to claim 1 , wherein said at least one conditional select instruction comprises an invert increment conditional select instruction, said operation comprising logically inverting said data element from said secondary source storage element and incrementing it to generate an arithmetic negation of said data element.

8. A data processing apparatus according to claim 1 , wherein said storage element data store comprises a storage element name that maps to a zero value.

9. A data processing apparatus according to claim 1 , wherein said storage elements comprise registers and said storage element data store comprises a register bank.

10. A data processing apparatus according to claim 1 , wherein said storage elements comprise memory locations and said storage element data store comprises a memory.

11. A data processing apparatus according to claim 1 , wherein
said instruction decoder is configured to output an increment control signal in response to said conditional select instruction; and
said processor configured to process said decoded conditional select instructions comprises:
an adder configured to receive values from said secondary storage element and a carry in signal;
a multiplexer configured to receive signals from said primary storage element and from an output of said adder, a select signal for said multiplexer comprising said condition, such that said condition having said predetermined outcome triggers said multiplexer to select said output of said adder; wherein
in response to said increment control signal being set, said carry in signal is set to one and said adder increments a received value from said at least one source storage element.

12. A data processing apparatus according to claim 11 ,
wherein said instruction decoder is configured to output an increment control signal and an invert control signal in response to said conditional select instruction; wherein
in response to said increment signal being set, said carry in signal is set to one and in response to said invert signal having being set said adder increments said received inverted value from said secondary source storage element.

13. A data processing apparatus according to claim 1 , wherein said primary source storage element and said secondary source storage element are a same storage element.

14. A data processing apparatus according to claim 1 , wherein an outcome of said condition is determined from arithmetic logic flags set in response to at least one previous data processing operation.

15. A data processing apparatus according to claim 14 , wherein sat at least one previous data processing operation comprises comparing a data element within at least one of said source storage elements with another value.

16. A data processing apparatus according to claim 15 , wherein said at least one previous data processing operation comprises comparing a data element in said primary source storage element with a data element in said secondary source element.

17. A data processing apparatus according to claim 14 , wherein said condition comprises at least one of not equal, equal, less than, greater than, greater than or equal, less than or equal, zero and negative.

18. A data processing apparatus according to claim 14 , wherein said arithmetic logic flags, comprise at least one of a result negative flag, a result zero flag, a carry out flag and a signed overflow flag.

19. A data processing apparatus according to claim 1 , wherein said predetermined outcome of said condition comprises said condition being met.

20. A data processing apparatus according to claim 1 , said conditional select instruction comprising an indicator indicating a width of said source and destination storage elements.

21. A data processing apparatus according to claim 1 , said data processing apparatus comprising arithmetic circuitry for performing add and subtract operations in re

Assignees

• Advanced Risc Mach Ltd

Inventors

• Craske Simon John
• Grisenthwaite Richard Roy
• Stephens Nigel John

Classifications

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title

• G06F9/30003 Primary

  Arrangements for executing specific machine instructions · CPC title

• G06F9/265 Primary

  by address selection on input of storage · CPC title