Control systems state vector management using co-processing and multiport ram

Patent metadata

Field	Value
Publication number	US-9983558-B2
Application number	US-201514720536-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	May 22, 2015
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

An integrated state vector management system for control systems includes a plurality of co-processors configured to generate and utilize state vector data. The integrated state vector management system further includes state vector module communicatively connected to each of the plurality of co-processors. The state vector module includes a state vector memory containing at least three memory buffers for storing three datasets of state vector data. The state vector module further includes a state vector memory control logic communicatively coupled to the state vector memory. The state vector control logic is configured to provide read and write control to the state vector memory. The state vector memory control logic includes at least a write pointer controller and a read pointer controller.

First claim

What is claimed is:

1. An integrated state vector management system for control systems comprising:
a plurality of co-processors configured to generate and utilize state vector data, each one of the plurality of co-processors is configured to maintain a map indicative of a subset of the state vector data utilized by the corresponding co-processor; and
a state vector module communicatively connected to each of the plurality of co-processors via two separate communication buses including a write bus and a read bus, the write bus and the read bus comprising a serial encoded bit stream circuit, wherein the state vector module comprises:
a state vector memory comprising at least three memory buffers for storing three datasets of state vector data, a first memory buffer of the at least three memory buffers comprising a read buffer, a second memory buffer of the at least three memory buffers comprising a write buffer and a third buffer of the at least three memory buffers is reserved for a future write operation; and
a state vector memory control logic communicatively coupled to the state vector memory, the state vector control logic configured to provide read and write control to the state vector memory, the state vector memory control logic comprising at least a write pointer controller and a read pointer controller.

2. The integrated system of claim 1 , wherein the read pointer controller is configured to read entire dataset of the state vector data from the read buffer and to broadcast the entire dataset of the state vector data via the read bus to each of the plurality of co-processors substantially simultaneously after a pre-determined period of time.

3. The integrated system of claim 1 , wherein each of the plurality of co-processors is configured to maintain at least a copy flag, a query flag and a valid flag utilized by the read pointer controller and write pointer controller during read and write operations.

4. The integrated system of claim 1 , wherein each of the plurality of co-processors is configured to maintain at least a first and second subsets of the state vector data wherein the first subset is stored in a local read buffer and the second subset is stored in a local write buffer of the corresponding co-processor and wherein the local write buffer is connected to the write bus and the local read buffer is connected to the read bus.

5. The integrated system of claim 4 , wherein the state vector module is configured to determine, after a predefined period of time, whether any of the plurality of co-processors contains a new subset of the state vector data in its local write buffer to write to the state vector memory and configured to, in response to identifying one or more co-processors ready to write the new subset of the state vector data, progressively select each of the plurality of co-processors for a write operation.

6. The integrated system of claim 5 , wherein the write operation comprises transmitting a subset of the state vector data from the local write buffer of the selected co-processor to the write buffer of the state vector module via the write bus.

7. The integrated system of claim 1 , wherein the plurality of coprocessors and the state vector module comprises at least one of an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA).

8. The integrated system of claim 1 , wherein the state vector data represents a state of the system at a particular time instance.

9. An integrated state vector management system for control systems comprising:
a plurality of sensors configured to acquire state vector data;
a plurality of co-processors communicatively coupled to the plurality of sensors, the plurality of co-processors including a hardware logic configured to control the acquisition of the state vector data, configured to analyze the state vector data and configured to maintain a map indicative of a subset of the state vector data utilized by the corresponding co-processor; and
a state vector module communicatively connected to each of the plurality of co-processors via two separate communication buses including a write bus and a read bus, the write bus and the read bus comprising a serial encoded bit stream circuit, wherein the state vector module comprises:
a state vector memory comprising at least three memory buffers for storing three datasets of state vector data, a first memory buffer of the at least three memory buffers comprising a read buffer, a second memory buffer of the at least three memory buffers comprising a write buffer and a third buffer of the at least three memory buffers is reserved for a future write operation; and
a state vector memory control logic communicatively coupled to the state vector memory, the state vector control logic configured to provide read and write control to the state vector memory, the state vector memory control logic comprising at least a write pointer controller and a read pointer controller.

10. The integrated system of claim 9 , wherein the state vector memory control logic provides read and write control to the state vector memory in a non-blocking manner.

11. The integrated system of claim 9 , wherein the state vector memory stores a plurality of state vector data values utilized by the plurality of co-processors.

12. The integrated system of claim 9 , wherein the plurality of coprocessors and the state vector module comprises at least one of an Application Specific Integrated Circuit (ASIC) and a Field Programmable Gate Array (FPGA).

13. The integrated system of claim 9 , wherein the state vector data represents a state of the system at a particular time instance.

Assignees

• Goodrich Corp

Inventors

• Rencs Erik V

Classifications

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G05B2219/15057

  FPGA field programmable gate array · CPC title

• G05B2219/25143

  Buffer for communication between two cpu · CPC title

• G05B19/0421 Primary

  Multiprocessor system · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title