Semiconductor device with improved variable gain amplification

Patent metadata

Field	Value
Publication number	US-9979364-B2
Application number	US-201715788505-A
Country	US
Kind code	B2
Filing date	Oct 19, 2017
Priority date	Apr 22, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

In a semiconductor device, a first variable gain amplifier and a second variable gain amplifier constitute a switched capacitor type variable gain amplifier. A selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and a load circuit such that the first variable gain amplifier and the load circuit are connected to each other when an amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first variable gain amplifier;
a second variable gain amplifier;
a load circuit including a capacitive load; and
a selection switch,
wherein the first variable gain amplifier includes a first sampling capacitance configured to hold a first voltage signal which is input, a first feedback capacitance, and a first operational amplifier, the first operational amplifier including a first input terminal and a first output terminal, the first input terminal being connected to the first sampling capacitance, and the first feedback capacitance being connected between the first input terminal and the first output terminal,
an amplification factor of the first variable gain amplifier is determined by a ratio between a capacitance value of the first sampling capacitance and a capacitance value of the first feedback capacitance,
the second variable gain amplifier includes a second sampling capacitance configured to sample a second voltage signal which is output from the first variable gain amplifier, a second feedback capacitance, and a second operational amplifier, the second operational amplifier including a second input terminal and a second output terminal, the second input terminal being connected to the second sampling capacitance, and the second feedback capacitance being connected between the second input terminal and the second output terminal,
an amplification factor of the second variable gain amplifier is determined by a ratio between a capacitance value of the second sampling capacitance and a capacitance value of the second feedback capacitance,
the first variable gain amplifier and the second variable gain amplifier constitute a switched capacitor type variable gain amplifier, and
the selection switch switches connection among the first variable gain amplifier, the second variable gain amplifier, and the load circuit such that the first variable gain amplifier and the load circuit are connected to each other when the amplification factor of the first variable gain amplifier is a predetermined gain or less, and the second variable gain amplifier is connected between the first variable gain amplifier and the load circuit when the amplification factor of the first variable gain amplifier is larger than the predetermined gain.

2. The semiconductor device according to claim 1 , further comprising:
a control circuit configured to halt the second variable gain amplifier when the amplification factor of the first variable gain amplifier is the predetermined gain or less.

3. The semiconductor device according to claim 1 , wherein the second variable gain amplifier is controlled so that sampling and amplifying of the second voltage signal are simultaneously performed.

4. The semiconductor device according to claim 3 , wherein the first variable gain amplifier and the second variable gain amplifier are fully differential amplifiers,
the first output terminal includes a first positive output terminal and a first negative output terminal,
the second input terminal includes a second positive input terminal and a second negative input terminal,
the second output terminal includes a second positive output terminal and a second negative output terminal,
when the amplification factor of the first variable gain amplifier is the predetermined gain or less, a signal which is output from the first positive output terminal is output as a positive output signal, and a signal which is output from the first negative output terminal is output as a negative output signal,
when the amplification factor of the first variable gain amplifier is larger than the predetermined gain, the first positive output terminal and the second positive input terminal are electrically connected to each other, and the first negative output terminal and the second negative input terminal are electrically connected to each other, and
when the amplification factor of the first variable gain amplifier is larger than the predetermined gain, a signal which is output from the second positive output terminal is output as the positive output signal, and a signal which is output from the second negative output terminal is output as the negative output signal.

5. The semiconductor device according to claim 1 , wherein the first variable gain amplifier and the second variable gain amplifier are fully differential amplifiers,
a common mode output voltage of the first operational amplifier is smaller than a common mode input voltage of the first operational amplifier, and
a common mode output voltage of the second operational amplifier is smaller than a common mode input voltage of the second operational amplifier.

6. The semiconductor device according to claim 1 , wherein the first sampling capacitance includes a first sub-sampling capacitance and a second sub-sampling capacitance,
the first sub-sampling capacitance holds a first signal level of the first voltage signal in a first period,
the second sub-sampling capacitance holds a second signal level of the first voltage signal in a second period which is different from the first period, and the second signal level is different from the first signal level, and
the first variable gain amplifier outputs a difference between the first signal level and the second signal level in a third period which is different from the first period and the second period.

7. The semiconductor device according to claim 6 , further comprising:
a pixel array in which a plurality of pixels configured to generate the first voltage signal in accordance with incident light are arranged in a matrix form,
wherein a plurality of the first sampling capacitances corresponding to a plurality of columns of the pixel array are arranged,
a plurality of the first sub-sampling capacitances simultaneously hold the first signal levels of the plurality of columns in the first period,
a plurality of the second sub-sampling capacitances simultaneously hold the second signal levels of the plurality of columns in the second period, and
the first variable gain amplifier sequentially outputs differences between the first signal levels and the second signal levels of the plurality of columns in the third period.

8. The semiconductor device according to claim 1 , wherein the capacitance value of the second sampling capacitance is set to be inversely proportional to a gain of the first variable gain amplifier.

9. The semiconductor device according to claim 1 , wherein the load circuit is an analog to digital (AD) converter including a sampling capacitance, and
the first variable gain amplifier, the second variable gain amplifier, the selection switch, and the load circuit are arranged in the same substrate.

Assignees

• Olympus Corp

Inventors

• Osawa Masato
• Harada Yasunari
• Kato Hideki

Classifications

• H03F1/26 Primary

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03F2200/45

  the load of the amplifier being a capacitive element, e.g. CRT · CPC title

• H03F2203/7231

  the gated amplifier being switched on or off by putting into cascade or not, by choosing between amplifiers by one or more switch(es) · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title