Switching mode power supply with adaptive frequency

Patent metadata

Field	Value
Publication number	US-9979288-B2
Application number	US-201715486235-A
Country	US
Kind code	B2
Filing date	Apr 12, 2017
Priority date	Apr 13, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Switching mode power supply (SMPS) having a switch circuit and a controller. The switch circuit has an output inductor and a switch with a minimum on time. A control signal is generated by the controller to control the switching operation of the switch based on a clock signal with a switching frequency and an off signal. When the required on time of the switch is smaller than the minimum on time, the SMPS reduces the switching frequency adaptively and the actual on time of the switch is controlled to be the minimum on time.

First claim

What is claimed is:

1. A controller for controlling a switching mode power supply (SMPS), wherein the SMPS comprises a switch with a minimum on time, and the SMPS converts an input voltage to an output voltage, the controller comprising:
a clock circuit, configured to generate a clock signal to control the turn on moment of the switch, wherein when the required on time of the switch for converting the input voltage to a target output voltage is bigger than the minimum on time, the frequency of the clock signal is controlled to be a preset frequency, when the required on time of the switch is smaller than the minimum on time, the frequency of the clock signal is controlled to be positively correlated to the required on time of the switch;
an off signal generator, configured to generate an off signal to control the actual on time of the switch, wherein when the required on time of the switch is bigger than the minimum on time, the actual on time of the switch is controlled to be the required on time of the switch, when the required on time of the switch is smaller than the minimum on time, the actual on time of the switch is controlled to be the minimum on time; and
a logic circuit, coupled to the clock circuit and the off signal generator, wherein the logic circuit is configured to control the switching operation of the switch based on the clock signal and the off signal.

2. The controller of claim 1 , wherein when the required on time of the switch is smaller than the minimum on time, the frequency of the clock signal is inversely correlated to the input voltage and positively correlated to the output voltage.

3. The controller of claim 1 , wherein the controller further comprises a module detection circuit configured to generate an indication signal based on the required on time of the switch and a minimum on time signal indicative of the minimum on time, and wherein the clock circuit is configured to generate the clock signal based on the indication signal.

4. The controller of claim 3 , wherein the clock circuit comprises:
a preset clock generator, configured to provide a preset clock signal with the preset frequency; and
a delay circuit, configured to receive the preset clock signal and the indication signal, and wherein when the indication signal indicates the required on time of the switch is bigger than the minimum on time, the preset clock signal is provided as the clock signal, when the indication signal indicates the required on time of the switch is smaller than the minimum on time, the effective edge of the preset signal is delayed for a period of time to form the clock signal.

5. The controller of claim 4 , wherein the indication signal is the off signal.

6. The controller of claim 1 , wherein the clock circuit comprises:
a current source, having a first terminal and a second terminal, wherein the first terminal is coupled to a supply voltage and the second terminal is configured to provide a current;
a capacitor, having a first terminal and a second terminal, wherein the first terminal is coupled to the second terminal of the current source, and the second terminal is coupled to a reference ground;
a switch transistor, having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the current source and the first terminal of the capacitor, the second terminal is coupled to the reference ground, and the control terminal is coupled to the clock signal;
a comparator, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the second terminal of the current source and the first terminal of the capacitor, the second input terminal is configured to receive a reference voltage, and the output terminal is configured to provide a comparing signal;
an inverter, having an input terminal and an output terminal, wherein the input terminal is coupled to the output terminal of the comparator to receive the comparing signal; and
a NOR gate, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the inverter, the second input terminal is coupled to an indication signal, and the output terminal is configured to provide the clock signal.

7. The controller of claim 1 , wherein the SMPS comprises an output inductor, the off signal generator comprises:
an amplifier, configured to generate an error amplified signal based on a reference signal and a feedback signal indicative of the output voltage;
a comparator, configured to generate a comparison signal based on the error amplified signal and an inductor current sense signal indicative of the inductor current flowing through the output inductor; and
an AND gate, having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the comparator to receive the comparison signal, the second input terminal is coupled to a minimum on time signal indicative of the minimum on time, and the output terminal is configured to provide the off signal.

8. The controller of claim 1 , wherein the SMPS comprises an output inductor, the off signal generator comprises:
an amplifier, configured to generate an error amplified signal based on a reference signal and a feedback signal indicative of the output voltage; and
a comparator, having a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is coupled to the error amplified signal, the second input terminal is coupled to an inductor current sense signal indicative of the inductor current flowing through the output inductor, and the control terminal is configured to receive a minimum on time signal indicative of the minimum on time, and wherein the comparator is configured to generate a comparison signal as the off signal based on the error amplified signal, the inductor current sense signal and the minimum on time signal, and wherein when the minimum on time signal is in an effective state, the off signal is in an ineffective state.

9. The controller of claim 1 , wherein the logic circuit comprises a RS-trigger coupled to the clock circuit and the off signal generator to respectively receive the clock signal and the off signal, and wherein the RS-trigger is configured to generate a control signal to control the switching operation of the switch based on the clock signal and the off signal.

10. A switching mode power supply (SMPS) for converting an input voltage to an output voltage, the SMPS comprising:
a switching circuit comprising a switch with a minimum on time; and
a controller, comprising:
a clock circuit, configured to generate a clock signal to control the turn on moment of the switch, wherein when the required on time of the switch for converting the input voltage to a target output voltage is bigger than the minimum on time, the frequency of the clock signal is controlled to be a preset frequency, when the required on time of the switch is smaller than the minimum on time, the frequency of the clock signal is controlled to be positively correlated to the required on time of the switch;
an off signal generator, configured to generate an off signal to control the actual on time of the switch, wherein when the required on time of the switch is bigger than the minimum on time, the actual on time of the switch is controlled to be the required on time of the switch, when the required on time of the switch is smaller than the minimum on time, the actual on time of the switch is controlled to be the minimum on time; and
a logic circuit, coupled to the clock circuit and the off

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Mao Wei
• Zhang Tianzhu

Classifications

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/157 Primary

  with digital control · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• H02M1/0041

  Control circuits in which a clock signal is selectively enabled or disabled · CPC title

• H02M1/00 Primary

  Details of apparatus for conversion · CPC title