Methods of manufacturing gallium nitride devices

Patent metadata

Field	Value
Publication number	US-9978858-B2
Application number	US-201715433473-A
Country	US
Kind code	B2
Filing date	Feb 15, 2017
Priority date	Dec 2, 2005
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Gallium nitride material devices and methods associated with the same. In some embodiments, the devices may be transistors which include a conductive structure connected to a source electrode. The conductive structure may form a source field plate which can be formed over a dielectric material and can extend in the direction of the gate electrode of the transistor. The source field plate may reduce the electrical field (e.g., peak electrical field and/or integrated electrical field) in the region of the device between the gate electrode and the drain electrode which can lead to a number of advantages including reduced gate-drain feedback capacitance, reduced surface electron concentration, increased breakdown voltage, and improved device reliability. These advantages enable the gallium nitride material transistors to operate at high drain efficiencies and/or high output powers. The devices can be used in RF power applications, amongst others.

First claim

What is claimed is:

1. A method, comprising:
forming a gallium nitride material region over a substrate;
forming a source electrode, at least in part, over the gallium nitride material region;
forming a gate electrode, at least in part, over the gallium nitride material region;
forming a drain electrode, at least in part, over the gallium nitride material region;
forming a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode;
forming a source field plate comprising a conductive material that is electrically connected to the source electrode;
forming a via which extends through the gallium nitride material and the substrate to a backside of the substrate;
forming a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and
forming a barrier layer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate,
wherein the barrier layer prevents chemical reactions between the conductive material and the substrate,
wherein the barrier layer comprises one or more of titanium, tungsten, nickel and platinum.

2. The method of claim 1 , wherein the source field plate extends over e gate electrode.

3. The method of claim 1 , further comprising:
forming an encapsulation layer over at least the gate electrode and the passivation layer.

4. The method of claim 3 , wherein the source field plate extends onto a surface of the encapsulation layer facing away from the substrate.

5. The method of claim 1 , wherein the source field plate is formed on a dielectric layer.

6. The method of claim 1 , wherein the source field plate is formed on the passivation layer.

7. The method of claim 1 , further comprising:
forming a gate electrode via in the passivation layer in which the gate electrode is formed.

8. The method of claim 7 , wherein a cross-sectional area at a top of the gate electrode via is greater than a cross-sectional area at a bottom of the gate electrode via.

9. The method of claim 1 , further comprising:
forming a compositionally-graded transition layer between the substrate and the gallium nitride material region.

10. The method of claim 1 , wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition.

11. The method of claim 1 , wherein the barrier layer comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different layers.

12. The method of claim 1 , wherein the barrier layer comprises a titanium-tungsten alloy.

13. A method of manufacturing a transistor unit cell, the method comprising:
forming a gallium nitride material region over a substrate;
forming a plurality of transistor building block structures, each transistor building block structure comprising:
a source electrode, at least in part, over the gallium nitride material region;
a gate electrode, at least in part, over the gallium nitride material region;
a drain electrode, at least in part, over the gallium nitride material region;
a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode;
a source field plate comprising a conductive material that is electrically connected to the source electrode;
a via which extends through the gallium nitride material and the substrate to a backside of the substrate;
a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and
a barrier layer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier layer comprising one or more of titanium, tungsten, nickel and platinum;

connecting the source electrodes in the transistor building block structures to a common source pad;
connecting the gate electrodes in the transistor building block structures to a common gate pad; and
connecting the drain electrodes in the transistor building block structures to a common drain pad.

14. The method of claim 13 , wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum alloyed to form a single composition.

15. The method of claim 13 , wherein the barrier layer in each transistor building block structure comprises more than one of titanium, tungsten, nickel and platinum formed as a series of different layers.

16. The method of claim 13 , wherein the barrier layer in each transistor building block structure comprises a titanium-tungsten alloy.

17. A method of manufacturing a power transistor, comprising:
forming a gallium nitride material region over a substrate;
forming a plurality of transistor unit cells arranged in parallel, each transistor unit cell comprising a plurality of transistor building block structures, each transistor building block structure comprising:
a source electrode, at least in part, over the gallium nitride material region;
a gate electrode, at least in part, over the gallium nitride material region;
a drain electrode, at least in part, over the gallium nitride material region;
a passivation layer over the gallium nitride material region between the source electrode and the gate electrode, and between the gate electrode and the drain electrode, the gate electrode extending over a portion of the passivation layer a distance directly on the passivation layer in a direction of the drain electrode greater than a distance in a direction of the source electrode;
a source field plate comprising a conductive material that is electrically connected to the source electrode;
a via which extends through the gallium nitride material and the substrate to a backside of the substrate;
a conductive material in the via and which electrically connects the source field plate to a conductive region at the backside of the substrate; and
a barrier layer on sidewalls of the via so as to separate the conductive material from the gallium nitride material region and the substrate, the barrier layer preventing chemical reactions between the conductive material and the substrate, the barrier layer comprising one or more of titanium, tungsten, nickel and platinum,
wherein the source electrodes in the transistor building block structures are connected to a common source pad in the respective transistor unit cells,
wherein the gate electrodes in the transistor building block structures are connected to a common gate pad in the respective transistor unit cells,
wherein the drain electrodes in the transistor building block structures are connected to a common drain pad in the respective transistor unit cells;

connecting the source pads in the transistor unit cells to a source bus;
connecting the drain pads in the transistor unit

Assignees

• Infineon Technologies Americas Corp

Inventors

• Johnson Jerry Wayne
• Singhal Sameer
• Hanson Allen W
• Therrien Robert Joseph

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/2003

  Electricity · mapped topic

• H01L29/7787 Primary

  Electricity · mapped topic

• H01L29/42316

  Electricity · mapped topic

• H01L29/41725

  Electricity · mapped topic